-
公开(公告)号：US12277969B2
公开(公告)日：2025-04-15
申请号：US18661300
申请日：2024-05-10
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Paolo Amato , Federico Pio , Alessandro Orlando , Marco Sforzin
Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.
-
公开(公告)号：US20250061023A1
公开(公告)日：2025-02-20
申请号：US18936548
申请日：2024-11-04
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Christophe Laurent , Riccardo Muzzetto
Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.
-
公开(公告)号：US20240393961A1
公开(公告)日：2024-11-28
申请号：US18794482
申请日：2024-08-05
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Corrado Villa , Andrea Martinelli , Christophe Vincent Antoine Laurent
IPC: G06F3/06
Abstract: A method to perform data scrub operations by operating a memory device, the memory device comprising a main memory, an internal Error Correction Code (ECC) engine and a scrub memory. The method comprising: receiving a read command; accessing, based on the receiving the read command, a location in the main memory to read data at the location; error correcting data read during the accessing; and storing at the scrub memory information of the location based at least in part on the correcting the data meeting or exceeding an ECC threshold.
-
公开(公告)号：US12135610B2
公开(公告)日：2024-11-05
申请号：US17802053
申请日：2021-09-23
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Christophe Laurent , Riccardo Muzzetto
Abstract: The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.
-
公开(公告)号：US20240061792A1
公开(公告)日：2024-02-22
申请号：US18235289
申请日：2023-08-17
Applicant: Micron Technology, Inc.
Inventor： Emanuele Confalonieri , Paolo Amato , Daniele Balluchi , Marco Sforzin , Danilo Caraccio , Niccolò Izzo , Graziano Mirichigni , Massimiliano Patriarca
IPC: G06F12/14 , G06F12/0804
CPC classification number: G06F12/1458 , G06F12/0804
Abstract: Systems, apparatuses, and methods related to data identity recognition for semiconductor devices are described. A system includes a host and a memory device coupled to the host via an interconnect bus. The host includes a host security manager configured to encrypt data of a command, perform a memory integrity check, allow access to memory of a memory device corresponding to an address of a command based on which entity associated with the host sent the command, generate security keys, program security keys into the memory device, program encryption ranges, or any combination thereof. The memory device includes a memory encryption manager and a memory device security manager. The memory device security manager is configured to detect whether a command was sent from a trusted domain of the host or non-trusted domain of the host and identify which entity associated with the host initiated the command.
-
Patent Agency Ranking
公开(公告)号：US11740678B2
公开(公告)日：2023-08-29
申请号：US17573194
申请日：2022-01-11
Applicant: Micron Technology, Inc.
IPC: G06F1/32 , G06F9/44 , G06F1/3225 , G06F1/3234 , G06F9/4401 , G06F1/3287
CPC classification number: G06F1/3225 , G06F1/3275 , G06F1/3287 , G06F9/4401
Abstract: Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.
-
公开(公告)号：US20230109794A1
公开(公告)日：2023-04-13
申请号：US18079515
申请日：2022-12-12
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Corrado Villa
IPC: G11C13/00
Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage to the memory array based on the read request. The control circuit is additionally configured to count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage and to apply a second voltage to the memory array based on the total number. The control circuit is further configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.
-
公开(公告)号：US11282574B2
公开(公告)日：2022-03-22
申请号：US17062127
申请日：2020-10-02
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Paolo Amato , Federico Pio , Alessandro Orlando , Marco Sforzin
Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.
-
公开(公告)号：US20220013157A1
公开(公告)日：2022-01-13
申请号：US17381976
申请日：2021-07-21
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Efrem Bolandrina
IPC: G11C8/08 , G06F3/06 , G11C11/22 , G11C11/408 , G11C7/10 , G11C7/22 , G11C11/4096
Abstract: Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may be associated with a respective local latching circuit, which may be used to maintain phases at the subarray independent of subsequent commands to the same bank. For example, the latching circuit may internalize timing signals triggered by a precharge command for a first row such that if an activation command is received for a different subarray in the same bank at a time before the precharge operation of the first row is complete, the precharge operation may continue until the first row is closed, as the timing signals triggered by the precharge command may be maintained locally at the subarray using the latching circuit.
-
公开(公告)号：US20210257022A1
公开(公告)日：2021-08-19
申请号：US17165579
申请日：2021-02-02
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Marco Sforzin , Alessandro Orlando
Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage. When the time duration expires, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.
-
-
-
-
-
-
-
-
-
Search Results
148
records
(took 0.032 seconds)
