公开(公告)号：US10854293B2

公开(公告)日：2020-12-01

申请号：US16868777

申请日：2020-05-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Han Zhao

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Methods of operating a memory include activating a respective memory cell of each string of series-connected memory cells of a plurality of strings of series-connected memory cells, selectively activating a target memory cell of a selected string of series-connected memory cells of the plurality of strings of series-connected memory cells depending upon its data state, and deactivating a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells.

公开(公告)号：US10770470B2

公开(公告)日：2020-09-08

申请号：US15457473

申请日：2017-03-13

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa ,  Tamotsu Murakoshi ,  Deepak Thimmegowda

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568

Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

公开(公告)号：US10484718B2

公开(公告)日：2019-11-19

申请号：US16197174

申请日：2018-11-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/06 ,  H04N19/86 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/08 ,  G11C16/10 ,  H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/61 ,  H04N19/80 ,  H04N19/82

Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US20190220196A1

公开(公告)日：2019-07-18

申请号：US16360115

申请日：2019-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G06F12/14

CPC classification number: G06F3/0604 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/14 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1052 ,  G06F2212/214 ,  G06F2212/2532 ,  Y02D10/14

Abstract: Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

公开(公告)号：US20190027194A1

公开(公告)日：2019-01-24

申请号：US16137309

申请日：2018-09-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/06 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11524 ,  G11C16/26 ,  G11C16/10 ,  G11C7/12 ,  G11C5/02 ,  G11C7/22 ,  G11C16/08 ,  G11C16/04 ,  G11C16/16

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US10170169B2

公开(公告)日：2019-01-01

申请号：US15720960

申请日：2017-09-29

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C8/10 ,  G11C7/02 ,  G11C8/12 ,  G11C8/16 ,  G11C11/408 ,  G11C7/00 ,  G11C13/00 ,  G11C8/18

Abstract: Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

公开(公告)号：US20180374937A1

公开(公告)日：2018-12-27

申请号：US16108899

申请日：2018-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/112

Abstract: Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

公开(公告)号：US20180357349A1

公开(公告)日：2018-12-13

申请号：US16105571

申请日：2018-08-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G06F17/50 ,  G11C7/10 ,  G11C29/02 ,  G11C13/00 ,  G11C7/22

CPC classification number: G06F17/5036 ,  G11C7/1066 ,  G11C7/227 ,  G11C13/0021 ,  G11C29/025

Abstract: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.

公开(公告)号：US20180315478A1

公开(公告)日：2018-11-01

申请号：US16021250

申请日：2018-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34

Abstract: Methods of programming and sensing in a memory device including connecting first and second data lines in series before programming or sensing, respectively.

公开(公告)号：US10083265B2

公开(公告)日：2018-09-25

申请号：US15061559

申请日：2016-03-04

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G06F17/50 ,  G11C13/00 ,  G11C29/02 ,  G11C7/22 ,  G11C7/10

CPC classification number: G06F17/5036 ,  G11C7/1066 ,  G11C7/227 ,  G11C13/0021 ,  G11C29/025

Abstract: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.