Methods for forming optoelectronic devices including heterojunction
    54.
    发明授权
    Methods for forming optoelectronic devices including heterojunction 有权
    用于形成包括异质结的光电器件的方法

    公开(公告)号:US09178099B2

    公开(公告)日:2015-11-03

    申请号:US13451439

    申请日:2012-04-19

    摘要: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

    摘要翻译: 实施例通常涉及诸如光伏电池的光电半导体器件。 一方面,用于形成器件的方法包括形成由砷化镓(GaAs)制成并具有一种类型的掺杂的吸收层,并形成由不同材料制成并具有比吸收层更高的带隙的发射极层。 可以在发射极和吸收层之间形成中间层。 在发射极层和吸收层之间形成异质结和p-n结,其中在与异质结偏离的位置处至少部分地在不同的材料内形成p-n结。 吸收层的大部分可以在由p-n结形成的耗尽区的外部。 p-n结导致电池响应于电池暴露于正面的光而产生电压。

    Methods for forming optoelectronic devices including heterojunction

    公开(公告)号:US09082919B2

    公开(公告)日:2015-07-14

    申请号:US13451439

    申请日:2012-04-19

    摘要: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

    Methods for forming optoelectronic devices including heterojunction

    公开(公告)号:US09048366B2

    公开(公告)日:2015-06-02

    申请号:US13451439

    申请日:2012-04-19

    摘要: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

    Method of fabricating a GaN P-i-N diode using implantation
    59.
    发明授权
    Method of fabricating a GaN P-i-N diode using implantation 有权
    使用注入制造GaN P-i-N二极管的方法

    公开(公告)号:US08822311B2

    公开(公告)日:2014-09-02

    申请号:US13335329

    申请日:2011-12-22

    IPC分类号: H01L29/20 H01L29/24

    摘要: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region.

    摘要翻译: III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。 有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区,并且包括包含第一III族氮化物外延材料的一部分的注入区。 第一III族氮化物外延材料的注入区域相对于与注入区域相邻的第一III族氮化物外延材料的部分具有降低的导电性。

    GAN vertical superjunction device structures and fabrication methods
    60.
    发明授权
    GAN vertical superjunction device structures and fabrication methods 有权
    GAN垂直超结装置结构及制造方法

    公开(公告)号:US08785975B2

    公开(公告)日:2014-07-22

    申请号:US13529822

    申请日:2012-06-21

    摘要: A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

    摘要翻译: 半导体器件包括第一导电类型的III族氮化物衬底,耦合到III族氮化物衬底的第一导电类型的第一III族氮化物外延层和耦合到第一III族氮化物外延结构的第一部分 第一III族氮化物外延层的表面。 第一III族氮化物外延结构具有侧壁。 半导体器件还包括耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构,第一导电类型的第二III族氮化物外延层耦合到第二III族氮化物外延的侧壁 层和第一III族氮化物外延层的表面的第二部分,以及耦合到第二III族氮化物外延层的第二导电类型的第三III族氮化物外延层。 半导体器件还包括耦合到第三III族氮化物外延层的表面的一个或多个电介质结构。