公开(公告)号：US08580660B2

公开(公告)日：2013-11-12

申请号：US13523603

申请日：2012-06-14

Applicant: Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66818

Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

Abstract translation: 双栅极金属氧化物半导体场效应晶体管（MOSFET）包括鳍状物，第一栅极和第二栅极。 第一个门形成在鳍的顶部。 第二个门围绕翅片和第一个门。 在另一实施方案中，三栅极MOSFET包括鳍片，第一栅极，第二栅极和第三栅极。 第一个门形成在鳍的顶部。 第二个门形成在翅片附近。 第三栅极形成在翅片附近并与第二栅极相对。

公开(公告)号：US07235436B1

公开(公告)日：2007-06-26

申请号：US10614051

申请日：2003-07-08

Applicant: Ming-Ren Lin ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC: H01L21/84

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for doping fin structures in FinFET devices includes forming a first glass layer on the fin structure of a first area and a second area. The method further includes removing the first glass layer from the second area, forming a second glass layer on the fin structure of the first area and the second area, and annealing the first area and the second area to dope the fin structures.

Abstract translation: 在FinFET器件中掺杂鳍结构的方法包括在第一区域和第二区域的鳍结构上形成第一玻璃层。 该方法还包括从第二区域去除第一玻璃层，在第一区域和第二区域的翅片结构上形成第二玻璃层，并退火第一区域和第二区域以掺杂翅片结构。

公开(公告)号：US07196374B1

公开(公告)日：2007-03-27

申请号：US10653274

申请日：2003-09-03

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78687

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract translation: 半导体器件包括衬底和衬底上的绝缘层。 半导体器件还包括形成在绝缘层上的翅片结构，其中鳍结构包括第一和第二侧表面，形成在鳍结构的第一和第二侧表面上的电介质层，形成在电介质层附近的第一栅电极 在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极，以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构 。

公开(公告)号：US06958264B1

公开(公告)日：2005-10-25

申请号：US09824933

申请日：2001-04-03

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21/322 ,  H01L21/335 ,  H01L21/8232

CPC classification number: H01L21/3221

Abstract: A method of manufacturing a semiconductor device on a silicon-on-insulator wafer including a silicon active layer having at least two die pads formed thereon, the at least two die pads separated by at least one scribe lane, including the steps of forming at least one cavity through the silicon active layer in the at least one scribe lane; forming at least one gettering plug in each said cavity, each said gettering plug comprising doped fill material containing a plurality of gettering sites; and subjecting the wafer to conditions to getter at least one impurity into the plurality of gettering sites. A silicon-on-insulator semiconductor wafer including a silicon active layer; a plurality of die pads formed in the silicon active layer; at least one scribe lane between and separating adjacent die pads; and at least one gettering plug in the at least one scribe lane, wherein the at least one gettering plug extends through the silicon active layer and the gettering plug comprises a doped fill material having a plurality of gettering sites.

Abstract translation: 一种在绝缘体上硅晶片上制造半导体器件的方法，其包括其上形成有至少两个管芯焊盘的硅有源层，所述至少两个管芯焊盘由至少一个划线通道隔开，包括至少形成 通过所述至少一个划线中的所述硅有源层的一个空腔; 在每个所述空腔中形成至少一个吸气塞，每个所述吸气塞包括含有多个吸气位点的掺杂填料; 并且使所述晶片经受条件以将至少一种杂质吸入所述多个吸气部位。 包括硅有源层的绝缘体上硅半导体晶片; 形成在所述硅有源层中的多个管芯焊盘; 在相邻的管芯焊盘之间和分离相邻的管芯焊盘之间的至少一个划线; 以及在所述至少一个划线中的至少一个吸气塞，其中所述至少一个吸气塞延伸穿过所述硅有源层，并且所述吸气塞包括具有多个吸气位点的掺杂填料。

公开(公告)号：US06812119B1

公开(公告)日：2004-11-02

申请号：US10614052

申请日：2003-07-08

Applicant: Shibly S. Ahmed ,  Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

IPC: H01L213205

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/7842

Abstract: A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first layer of semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.

Abstract translation: 一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。 该方法还包括在每个双盖的侧面上形成间隔物，并在双重帽下面的第一半导体材料层中形成双翅片。 该方法还包括使双翅片变薄以产生窄的双翅片。

公开(公告)号：US06790782B1

公开(公告)日：2004-09-14

申请号：US10157450

申请日：2002-05-29

Applicant: Chih-Yuh Yang ,  Cyrus E. Tabery ,  Ming-Ren Lin

Inventor： Chih-Yuh Yang ,  Cyrus E. Tabery ,  Ming-Ren Lin

IPC: H01L21302

CPC classification number: H01L21/28123 ,  H01L21/0337 ,  H01L21/28273 ,  H01L29/517

Abstract: The invention provides a method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack etch, and removal of exposed regions of the high-K dielectric to be performed efficiently in a single etch chamber. As such, process complexity and processing costs are reduced while throughput and overall process efficiency is improved. The method includes fabricating a high-K gate dielectric etch stop dielectric layer on the surface of a silicon substrate to protect the silicon substrate from erosion during an etch step and to prove a gate dielectric. A polysilicon layer is fabricated above the high-K dielectric layer. An anti-reflective coating layer above the polysilicon layer, and a mask is fabricated above the anti-reflective coating layer to define a gate region and an erosion region. The sequence of etching steps discussed above are performed in-situ in an enclosed high density plasma etching chamber environment.

Abstract translation: 本发明提供了在高K栅极电介质的表面上形成小几何形状的栅极的方法。 该方法提供了处理步骤，其包括在单个蚀刻室中有效执行的栅极图案修整，栅极堆叠蚀刻和去除高K电介质的暴露区域。 因此，降低了处理复杂性和处理成本，同时提高了吞吐量和整体处理效率。 该方法包括在硅衬底的表面上制造高K栅电介质蚀刻阻挡介电层，以在蚀刻步骤期间保护硅衬底免受腐蚀并证明栅极电介质。 在高K电介质层上方制造多晶硅层。 在多晶硅层上方的抗反射涂层和在抗反射涂层上方制造掩模以限定栅极区域和侵蚀区域。 上述蚀刻步骤的顺序在封闭的高密度等离子体蚀刻室环境中原位进行。

公开(公告)号：US06787864B2

公开(公告)日：2004-09-07

申请号：US10335492

申请日：2002-12-31

Applicant: Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

Inventor： Eric N. Paton ,  Qi Xiang ,  Paul R. Besser ,  Ming-Ren Lin ,  Minh V. Ngo ,  Haihong Wang

IPC: H01L2972

CPC classification number: H01L29/4933 ,  H01L21/28052 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

公开(公告)号：US06437404B1

公开(公告)日：2002-08-20

申请号：US09636239

申请日：2000-08-10

Applicant: Qi Xiang ,  Wei Long ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

IPC: H01L2701

CPC classification number: H01L29/78696 ,  H01L21/26533 ,  H01L21/28079 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78603

Abstract: A fully-depleted semiconductor-on-insulator (SOI) transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the layer. A gate is formed on a thin semiconductor layer between the top surface and the shallow portion of the insulator layer. Source and drain regions are formed on either side of the gate, the source and drain regions each being atop one of the deep portions of the buried insulator layer. The source and drain regions thereby have a greater thickness than the thin semiconductor layer. Thick silicide regions formed in the source and drain regions have low parasitic resistance. A method of making the transistor device includes forming a dummy gate structure on an SOI substrate, and using the dummy gate structure to control the depth of an implantation to form the nonuniform depth buried insulator layer.

Abstract translation: 完全耗尽的绝缘体上半导体（SOI）晶体管器件具有SOI衬底，其具有相对于衬底的顶表面具有不均匀深度的掩埋绝缘体层，所述掩埋绝缘体层具有靠近顶表面的较浅部分比 层的深部分。 栅极形成在绝缘体层的顶表面和浅部之间的薄半导体层上。 源极和漏极区域形成在栅极的任一侧上，源极和漏极区域分别位于掩埋绝缘体层的深部之一的顶部。 源极和漏极区域因此具有比薄的半导体层更大的厚度。 形成在源区和漏区的厚硅化物区具有低寄生电阻。 制造晶体管器件的方法包括在SOI衬底上形成虚拟栅极结构，并且使用虚拟栅极结构来控制注入的深度以形成不均匀深度的掩埋绝缘体层。

公开(公告)号：US06369429B1

公开(公告)日：2002-04-09

申请号：US09641727

申请日：2000-08-21

Applicant: Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

Inventor： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

IPC: H01L2352

CPC classification number: H01L21/28518 ,  H01L21/28568

Abstract: Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

Abstract translation: 通过选择性地沉积反应阻挡层并在反应阻挡层上选择性地沉积金属层，在源/漏区和栅电极上形成低电阻触点。 实施方案包括选择性沉积钴和钨的合金，其用作反应阻挡层，防止选择性沉积在其上的镍或钴层的硅化。 实施例还包括定制钴钨合金的组成，使得在其下形成薄的硅化物层以降低接触电阻。

公开(公告)号：US06362055B1

公开(公告)日：2002-03-26

申请号：US09144527

申请日：1998-08-31

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L218234

Abstract: A semiconductor device includes a first gate stack and a second gate stack, each gate stack corresponding to a gate of a FET formed on the semiconductor device. The first gate stack includes a gate material formed from one of poly-silicon, poly-SiGe, and amorphous silicon. The gate material is implanted with a dopant of a first conductivity type at a first concentration. A metal silicide layer is formed over the doped gate material. The second gate stack includes a gate material formed from one of poly-silicon, poly-Si—Ge, and amorphous silicon. The gate material of the second gate stack is implanted with a dopant of a second conductivity type at a second concentration.