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188 条记录 (耗时 0.025 秒)

    Strained transistor integration for CMOS
    51.
    发明申请
    Strained transistor integration for CMOS 失效
    用于CMOS的应变晶体管集成

    公开(公告)号：US20050136584A1

    公开(公告)日：2005-06-23

    申请号：US10747321

    申请日：2003-12-23

    申请人： Boyan Boyanov ,  Anand Murthy ,  Brian Doyle ,  Robert Chau

    发明人： Boyan Boyanov ,  Anand Murthy ,  Brian Doyle ,  Robert Chau

    IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L31/0328 ,  H01L21/8238

    CPC分类号： H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

    摘要： Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

    摘要翻译： 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

    Method of making MOSFET gate electrodes with tuned work function
    52.
    发明授权
    Method of making MOSFET gate electrodes with tuned work function 有权
    制造具有调谐功能的MOSFET栅电极的方法

    公开(公告)号：US06794232B2

    公开(公告)日：2004-09-21

    申请号：US10383842

    申请日：2003-03-07

    申请人： Jun-Fei Zheng ,  Brian Doyle ,  Gang Bai ,  Chunlin Liang

    发明人： Jun-Fei Zheng ,  Brian Doyle ,  Gang Bai ,  Chunlin Liang

    IPC分类号： H01I21337

    CPC分类号： H01L21/82345 ,  H01L21/823425 ,  H01L27/088

    摘要： Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

    摘要翻译： 具有至少两层材料的栅电极的绝缘栅场效应晶体管提供类似于掺杂多晶硅的栅电极功函数值，消除多余耗效应并且还基本上防止杂质扩散入栅电介质。 公开了用于n沟道FET的相对厚的Al和薄TiN的双层堆叠以及相对厚的Pd和薄TiN的双层堆叠，或者用于p沟道FET的相对厚的Pd和薄TaN。 改变第一和第二临界厚度之间的薄TiN或TaN层的厚度可以用于调制栅电极的功函数，从而在FET中的沟道掺杂和驱动电流之间获得期望的权衡。

    Transistor structure having silicide source/drain extensions
    53.
    发明授权
    Transistor structure having silicide source/drain extensions 有权
    具有硅化物源极/漏极延伸部的晶体管结构

    公开(公告)号：US06737710B2

    公开(公告)日：2004-05-18

    申请号：US09343293

    申请日：1999-06-30

    申请人： Peng Cheng ,  Brian Doyle ,  Gang Bai

    发明人： Peng Cheng ,  Brian Doyle ,  Gang Bai

    IPC分类号： H01L2976

    CPC分类号： H01L29/66507 ,  H01L29/41775

    摘要： A MOSFET includes a double silicided source/drain structure wherein the source/drain terminals include a silicided source/drain extension, a deep silicided source/drain region, and a doped semiconductor portion that surrounds a portion of the source/drain structure such that the suicides are isolated from the MOSFET body node. In a further aspect of the present invention, a barrier layer is formed around a gate electrode to prevent electrical shorts between a silicided source/drain extension and the gate electrode. A deep source/drain is then formed, self-aligned to sidewall spacers that are formed subsequent to the silicidation of the source/drain extension.

    摘要翻译： MOSFET包括双硅化物源极/漏极结构，其中源极/漏极端子包括硅化源极/漏极延伸部分，深硅化物源极/漏极区域以及围绕源极/漏极结构的一部分的掺杂半导体部分，使得 自杀从MOSFET体节点隔离。 在本发明的另一方面，在栅极周围形成阻挡层，以防止硅化物源极/漏极延伸部和栅电极之间的电短路。 然后形成深源/漏极，自对准到在源极/漏极延伸层的硅化之后形成的侧壁间隔物。

    Method for forming a High dielectric constant insulator in the fabrication of an integrated circuit
    55.
    发明授权
    Method for forming a High dielectric constant insulator in the fabrication of an integrated circuit 失效
    在制造集成电路中形成高介电常数绝缘体的方法

    公开(公告)号：US5891798A

    公开(公告)日：1999-04-06

    申请号：US771304

    申请日：1996-12-20

    申请人： Brian Doyle ,  Jack Lee

    发明人： Brian Doyle ,  Jack Lee

    IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

    CPC分类号： H01L21/28185 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L29/4916 ,  H01L29/518 ,  H01L21/26506 ,  H01L21/28079 ,  H01L21/28088

    摘要： A method for forming an insulator with a high dielectric constant on silicon is disclosed. This method overcomes one limitation of increasing the dielectric constant of a gate dielectric by using a high dielectric constant material, such as a paraelectric material, instead of silicon dioxide. First, nitrogen is implanted into the silicon through a sacrificial oxide layer. After annealing the substrate and stripping the sacrificial oxide, a dielectric layer is formed from a material with a high dielectric constant, such as a paraelectric material. Although the paraelectric material provides a source of oxygen for oxidation of silicon in subsequent high temperature process steps, no oxidation takes place due to the presence of the nitrogen in the silicon. Therefore, there is no undesired decrease in the overall capacitance of the dielectric system. When a gate electrode is formed on the dielectric layer, a nitrogen implant into the gate electrode can be used to prevent oxidation at the upper interface of the gate dielectric.

    摘要翻译： 公开了一种在硅上形成具有高介电常数的绝缘体的方法。 该方法克服了通过使用诸如顺电材料的高介电常数材料代替二氧化硅来增加栅极电介质的介电常数的一个限制。 首先，氮通过牺牲氧化物层注入到硅中。 在对衬底退火并剥离牺牲氧化物之后，介电层由具有高介电常数的材料（例如顺电材料）形成。 虽然在随后的高温工艺步骤中，顺电材料提供氧气用于氧化硅，但是由于硅中存在氮而不发生氧化。 因此，电介质系统的总电容不会有不期望的降低。 当在电介质层上形成栅电极时，可以使用栅极电极中的氮注入来防止栅电介质的上界面处的氧化。

    Alignment Guides for Constructing Building Components
    58.
    发明申请
    Alignment Guides for Constructing Building Components 审中-公开
    构建建筑构件的对齐指南

    公开(公告)号：US20150096185A1

    公开(公告)日：2015-04-09

    申请号：US14048939

    申请日：2013-10-08

    申请人： Brian Doyle

    发明人： Brian Doyle

    IPC分类号： E04F21/00 ,  G01B5/25

    CPC分类号： E04C2/34 ,  E04C2/246 ,  E04C2/44 ,  E04C2002/3488 ,  E04F21/003 ,  E04G21/1841 ,  G01B5/25 ,  Y10T29/49627

    摘要： The invention pertains to the field of construction of buildings and structures. The invention relates to alignment guides for constructing building components, namely walls, ceilings and floors to be used in buildings and structures. This invention also relates to kits of specific alignment guides and methods of using alignment guides.

    摘要翻译： 本发明涉及建筑物和结构的建造领域。 本发明涉及用于构建建筑构件的对准引导件，即用于建筑物和结构中的墙壁，天花板和地板。 本发明还涉及特定对准引导件的套件和使用对准引导件的方法。

    HIGH STABILITY SPINTRONIC MEMORY
    59.
    发明申请
    HIGH STABILITY SPINTRONIC MEMORY 有权
    高稳定性SPINTRONIC记忆

    公开(公告)号：US20140291663A1

    公开(公告)日：2014-10-02

    申请号：US13996603

    申请日：2013-03-28

    申请人： Charles Kuo ,  Kaan Oguz ,  Brian Doyle ,  Elijah Ilya Karpov ,  Roksana Golizadeh Mojarad ,  David Kencke ,  Robert Chau

    发明人： Charles Kuo ,  Kaan Oguz ,  Brian Doyle ,  Elijah Ilya Karpov ,  Roksana Golizadeh Mojarad ,  David Kencke ,  Robert Chau

    IPC分类号： H01L43/10 ,  H01L43/12

    CPC分类号： H01L43/10 ,  G11C11/161 ,  H01F10/3286 ,  H01F10/329 ,  H01L43/065 ,  H01L43/08 ,  H01L43/12 ,  H01L43/14

    摘要： An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.

    摘要翻译： 实施例包括在自由层和固定层之间包括自由磁性层，固定磁性层和隧道势垒的磁性隧道结（MTJ）; 所述隧道势垒直接接触所述自由层的第一侧; 和直接接触自由层的第二面的氧化物层; 其中所述隧道势垒包括氧化物并且具有第一电阻区域（RA）产物，并且所述氧化物层具有低于所述第一RA产物的第二RA产物。 MTJ可以包括在垂直旋转扭矩传递存储器中。 隧道势垒和氧化物层形成具有高稳定性的存储器，RA产物实质上高于具有仅具有单一氧化物层的MTJ的较少表存储器。 本文描述了其它实施例。