公开(公告)号：US20120074976A1

公开(公告)日：2012-03-29

申请号：US13247981

申请日：2011-09-28

Applicant: Aaron Durbin ,  David Keith ,  Morgan T. Johnson

Inventor： Aaron Durbin ,  David Keith ,  Morgan T. Johnson

IPC: G01R31/20

CPC classification number: G01R1/07378 ,  G01R1/04 ,  G01R1/0408 ,  G01R1/0491 ,  G01R31/2601 ,  G01R31/2607 ,  G01R31/2886 ,  G01R31/2889

Abstract: A wafer testing system and associated methods of use and manufacture are disclosed herein. In one embodiment, the wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways.

Abstract translation: 本文公开了晶片测试系统及其相关的使用和制造方法。 在一个实施例中，晶片测试系统包括用于通过单独可操作的真空或压力差将晶片可释放地附接到晶片转换器和晶片转换器到组件。 组件包括耦合到晶片转换器的晶片转换器支撑环，其中第一柔性材料从晶片转换器支撑环延伸，以便包围晶片转换器和插入器之间的空间，使得空间可以被第一真空抽真空 通过一个或多个第一疏散路径。 组件还可以包括耦合到晶片和卡盘的晶片支撑环，其中第二柔性材料从晶片支撑环延伸，以便包围晶片和晶片转换器之间的空间，使得空间可被第二个 通过一个或多个第二排空路径进行真空。

公开(公告)号：US08076216B2

公开(公告)日：2011-12-13

申请号：US12617691

申请日：2009-11-12

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: H01L21/00

CPC classification number: G01R31/2889 ,  G01R1/07307 ,  G01R31/2601 ,  H01L21/67 ,  H01L21/67253 ,  H01L21/6835 ,  H01L21/6838 ,  H01L21/76256 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2924/014

Abstract: A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated.

Abstract translation: 晶片转换器设置有晶片接合热固性塑料的图案化层，并且可拆卸地与晶片连接，以便形成晶片/晶片转换器对。 晶片转换器在薄化工艺期间以及在晶片切割操作期间用作机械支撑。 然后将单片化的集成电路从晶片转换器移除。 在一些实施例中，在晶片减薄处理之后但在晶片和晶片转换器分离之前执行晶片上的集成电路的晶片级测试。 在其他实施例中，在晶片切割操作之后，但是在切割的晶片和晶片转换器分离之前执行晶片上的集成电路的晶片级测试。

公开(公告)号：US20110050274A1

公开(公告)日：2011-03-03

申请号：US12547418

申请日：2009-08-25

Applicant: Aaron Durbin ,  Morgan T. Johnson ,  Jose A. Santos

Inventor： Aaron Durbin ,  Morgan T. Johnson ,  Jose A. Santos

IPC: G01R31/02 ,  G01R1/067 ,  G01R31/26

CPC classification number: G01R31/2601 ,  G01R31/2886

Abstract: A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair. In this way, no gasket is required to be disposed between the wafer and the wafer translator. Air, or gas, is evacuated from between the wafer and wafer translator through one or more evacuation pathways in the gasketless sealing means.

Abstract translation: 晶片转换器和可移除地彼此连接的晶片提供与晶片上的集成电路上的电触点的电连接，使得在制造这种电连接的过程中电触头基本上没有损坏。 本发明的各种实施例提供了一种无垫圈密封装置，用于通过真空附接晶片/晶片转换器对来促进形成。 以这种方式，不需要在晶片和晶片转换器之间设置衬垫。 空气或气体通过无垫圈密封装置中的一个或多个抽空通道从晶片和晶片转换器之间排出。

公开(公告)号：US07786745B2

公开(公告)日：2010-08-31

申请号：US12347995

申请日：2008-12-31

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02

CPC classification number: H01R12/79 ,  G01R31/2886

Abstract: An apparatus for providing electrical pathways between one or more unsingulated integrated circuits and one or more test circuits external to the integrated circuits, includes a flexible substrate having a first major surface and a second major surface, a plurality of first contact structures disposed in a central portion of the first surface of the flexible substrate, a plurality of second contact structures disposed in a peripheral annular region of the first surface of the flexible substrate, and a plurality of first electrically conductive pathways, each of the plurality of first electrically conductive pathways coupled to a respective first and second contact structure, wherein the second surface is free from first contact structures, second contact structures, and first electrically conductive pathways.

Abstract translation: 一种用于在一个或多个未设计的集成电路和集成电路外部的一个或多个测试电路之间提供电路径的装置包括具有第一主表面和第二主表面的柔性衬底，多个第一接触结构，其设置在中心 柔性基板的第一表面的一部分，设置在柔性基板的第一表面的周边环形区域中的多个第二接触结构，以及多个第一导电通路，多个第一导电通路中的每一个耦接 到相应的第一和第二接触结构，其中第二表面没有第一接触结构，第二接触结构和第一导电通路。

公开(公告)号：US20100066395A1

公开(公告)日：2010-03-18

申请号：US12404277

申请日：2009-03-13

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02

CPC classification number: G01R1/07371 ,  G01R1/04 ,  G01R1/0408 ,  G01R1/07314 ,  G01R1/07342 ,  G01R31/2887 ,  G01R31/2889

Abstract: Methods and apparatus for testing unsingulated integrated circuits on a wafer include adapting a wafer prober for use with full-wafer-contacter disposed on the wafer. Some embodiments include placing wafer on a chuck of the prober, aligning the wafer to a full-wafer contacter incorporated in the wafer prober, removably attaching the wafer to the full wafer contacter, separating the wafer from the chuck, and making electrical contact to one or more integrated circuits of the wafer by making physical contact with a surface of the full-wafer contacter that faces away from the wafer.

Abstract translation: 用于测试晶片上的非镶嵌集成电路的方法和装置包括使晶片探针适配用于设置在晶片上的全晶圆封装。 一些实施例包括将晶片放置在探测器的卡盘上，将晶片对准结晶在晶圆探针中的全晶圆接头，将晶片可移除地附接到全晶片连接器，将晶片与卡盘分离，并将电接触到一个 或更多的集成电路，通过与全晶圆连接器的远离​​晶片的表面进行物理接触。

公开(公告)号：US20100001749A1

公开(公告)日：2010-01-07

申请号：US12349187

申请日：2009-01-06

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R31/2884 ,  G01R31/2851 ,  G01R31/2853 ,  G01R31/2855

Abstract: An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs.

Abstract translation: 一种适于将晶片上的集成电路的焊盘与测试系统中的浮标塔的弹簧销耦合而不需要探针卡的装置包括具有第一表面和第二表面的本体，该主体具有基本上 圆形中心部分和从中心部分向外延伸的多个可弯曲臂，每个可弯曲臂具有设置在其远端处的连接片; 设置在所述主体的中心部分的第二表面上的第一多个接触端子，所述第一多个接触端子以图案布置以匹配待接触的晶片上的焊盘的布局; 至少一个接触端子，设置在所述多个连接器接头的第一表面上; 以及设置在所述主体中的多个导电通路，使得所述第一多个接触端子中的每一个电连接到所述连接器接头的第一表面上的对应的一个接触端子。

公开(公告)号：US20090244526A1

公开(公告)日：2009-10-01

申请号：US12326093

申请日：2008-12-01

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01J1/12

CPC classification number: G02B6/4222 ,  G01R31/2891 ,  G02B6/04 ,  G02B6/4226 ,  G02B6/4227

Abstract: A low-cost alignment system suitable for aligning a wafer to a test fixture includes a bundle of optical fibers wherein at least one fiber serves to deliver illumination to the alignment target from an end thereof, and a plurality of receiver fibers, each having ends with a known spatial relationship to the end of the illuminator fiber. The ends of the fiber bundle have a known spatial relationship to the fixture. In some embodiments, the fiber bundle is disposed within the fixture such that there is an unobscured optical path between the wafer and the receiving and illuminating ends of the fibers. In some embodiments, the fiber bundle is coupled to a light source and a light sensor mounted on the fixture. In some embodiments the alignment target is one or more bonding pads disposed on a wafer.

Abstract translation: 适用于将晶片对准测试夹具的低成本对准系统包括一束光纤，其中至少一根光纤用于从其端部向对准目标物发射照明，以及多个接收器光纤，每个接收器光纤 与照明器光纤末端的已知空间关系。 纤维束的端部与夹具具有已知的空间关系。 在一些实施例中，纤维束设置在固定装置内，使得在晶片与纤维的接收和照射端之间存在视觉上的光路。 在一些实施例中，光纤束耦合到安装在固定装置上的光源和光传感器。 在一些实施例中，对准靶是设置在晶片上的一个或多个接合焊盘。

公开(公告)号：US20090224372A1

公开(公告)日：2009-09-10

申请号：US12077670

申请日：2008-03-20

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L23/481 ,  G01R1/07342 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49139 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Apparatus and methods are provided for wafer translators having a silicon core, an isolating conductive ground plane, and copper and subjacent resin layers disposed on the ground plane. A silicon substrate having at least one major surface coated with an electrically conductive layer is subjected to a number of printed circuit board manufacturing operations including, but not limited to, application of resin-coated copper foils; mechanical grinding of copper layers; mechanical drilling of via openings in a dielectric material; plating of copper, nickel, and gold layers; laser removal of metal; and chemical removal of metal; in order to produce a wafer translator having a silicon core. In further aspects of the present invention, alignment marks are formed and contact structures, such as stud bumps, are placed relative to a local set of alignment marks.

Abstract translation: 提供了用于具有硅芯，隔离导电接地平面以及设置在接地平面上的铜和相邻树脂层的晶片转换器的装置和方法。 具有涂覆有导电层的至少一个主表面的硅衬底经受许多印刷电路板制造操作，包括但不限于施加树脂涂覆的铜箔; 铜层机械研磨; 电介质材料中通孔的机械钻孔; 电镀铜，镍和金层; 激光去除金属; 并化学除去金属; 以产生具有硅芯的晶片转换器。 在本发明的另外的方面，形成对准标记，并且相对于本地对准标记集合放置诸如柱形凸起的接触结构。

公开(公告)号：US07572132B2

公开(公告)日：2009-08-11

申请号：US11879736

申请日：2007-07-17

Applicant: Morgan T. Johnson ,  Peter H. Decher

Inventor： Morgan T. Johnson ,  Peter H. Decher

IPC: H01R13/62

CPC classification number: G01R31/2889

Abstract: A flexible extension wafer translator includes a wafer translator portion, one or more flexible connectors extending outwardly therefrom, and a connector tab coupled to the distal end of each outwardly extending flexible connector. The flexible connectors may take any suitable form, including but not limited to, draped and pleated.

Abstract translation: 柔性延伸晶片转换器包括晶片转换器部分，从其向外延伸的一个或多个柔性连接器，以及耦合到每个向外延伸的柔性连接器的远端的连接片。 柔性连接器可以采取任何合适的形式，包括但不限于披盖和打褶。

公开(公告)号：US20080230927A1

公开(公告)日：2008-09-25

申请号：US12079159

申请日：2008-03-24

Applicant: Morgan T. Johnson ,  Raymond J. Werner

Inventor： Morgan T. Johnson ,  Raymond J. Werner

IPC: H01L23/50 ,  H01L21/02

CPC classification number: G01R31/2884 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for producing fully tested unsingulated integrated circuits without probe scrub damage to bond pads includes forming a wafer/wafer translator pair removably attached to each other wherein the wafer translator includes contact structures formed from a soft crushable electrically conductive material and these contact structures are brought into contact with the bond pads in the presence of an inert gas; and subsequently a vacuum is drawn between the wafer and the wafer translator. In one aspect of the present invention, the unsingulated integrated circuits are exercised by a plurality of test systems wherein the bond pads are never physically touched by the test system and electrical access to the wafer is only provided through the inquiry-side of the wafer translator. In a further aspect of the present invention, known good die having bond pads without probe scrub marks are provided for incorporation into products.

Abstract translation: 用于生产完全被测试的非镶嵌集成电路的方法和装置，不对接合焊盘进行探针磨损损伤包括形成可移除地彼此附接的晶片/晶片转换器对，其中晶片转换器包括由软的可压电导电材料形成的接触结构，并且这些接触结构 在惰性气体存在下与接合垫接触; 随后在晶片和晶片转换器之间抽真空。 在本发明的一个方面中，由多个测试系统来执行无调制的集成电路，其中接合焊盘从未被测试系统物理地接触，并且仅通过晶片转换器的查询侧提供对晶片的电接触 。 在本发明的另一方面，提供了具有不具有探针擦洗痕的接合垫的已知的良好的模头用于结合到产品中。