Readout architecture for indirect time-of-flight sensing

    公开(公告)号:US11770633B2

    公开(公告)日:2023-09-26

    申请号:US17513064

    申请日:2021-10-28

    Abstract: A time-of-flight sensor includes a pixel array of pixel circuits. A first subset of the pixel circuits is illuminated by reflected modulated light from a portion of an object. A second subset of the pixel circuits is non-illuminated by the reflected modulated light. Each pixel circuit includes a floating diffusion that stores a portion of charge photogenerated in a photodiode in response to the reflected modulated light. A transfer transistor transfers the portion of charge from the photodiode to the floating diffusion in response to modulation by a phase modulation signal. A modulation driver block generates the phase modulation signal and is coupled to a light source that emits the modulated light to the portion of the object. The modulation driver block synchronizes scanning the modulated light emitted by the light source across the object with scanning of the first subset of the pixel circuits across the pixel array.

    Resettle timing for low power pixel readout

    公开(公告)号:US11683611B1

    公开(公告)日:2023-06-20

    申请号:US17714738

    申请日:2022-04-06

    Inventor: Zheng Yang Ling Fu

    CPC classification number: H04N25/75 H04N25/709 H04N25/772

    Abstract: A pixel readout circuit includes an analog to digital converter coupled to the bitline output of the pixel circuit. A switch is coupled between the bitline output of the pixel circuit and a reference voltage. The switch is pulsed on and off a first time to settle the bitline to the reference voltage prior to an autozero operation of the analog to digital converter. The switch is pulsed on and off a second time to settle the bitline to the reference voltage after the autozero operation and prior to a first analog to digital conversion. The switch is configured to be pulsed on and off a third time to settle the bitline to the reference voltage after the first analog to digital conversion operation and prior to a second analog to digital conversion operation.

    Differential Subrange ADC for Image Sensor
    53.
    发明公开

    公开(公告)号:US20230179889A1

    公开(公告)日:2023-06-08

    申请号:US17540434

    申请日:2021-12-02

    CPC classification number: H04N5/37455 H03M1/468 H03M1/462 H03M1/56 H04N5/378

    Abstract: A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.

    COLOR-INFRARED SENSOR WITH A LOW POWER BINNING READOUT MODE

    公开(公告)号:US20230035728A1

    公开(公告)日:2023-02-02

    申请号:US17388876

    申请日:2021-07-29

    Inventor: Zheng Yang

    Abstract: An imaging device includes a pixel array including a 4x4 grouping of pixel circuits. The 4x4 grouping of pixel circuits includes four rows and four columns of the pixel array. A plurality of bitlines includes a first bitline, a second bitline, a third bitline, and a fourth bitline. Each one of the first, second, third, and fourth bitlines is coupled to a respective four pixel circuits in the 4x4 grouping of pixel circuits. Each one of the first, second, third, and fourth bitlines is coupled to all four of the rows and to all four of the columns of the 4x4 grouping of pixel circuits.

    Bitline control supporting binning mode phase detection autofocus photodiodes

    公开(公告)号:US11463640B1

    公开(公告)日:2022-10-04

    申请号:US17339701

    申请日:2021-06-04

    Inventor: Rui Wang Zheng Yang

    Abstract: An imaging device includes pixel circuits that include either image sensing photodiodes or phase detection autofocus (PDAF) photodiodes. The PDAF photodiodes are included in a first PDAF pixel circuit included in a first grouping of rows, and a second PDAF pixel circuit included in a second grouping of rows of a pixel array. Bitline pairs are coupled to respective columns of the pixel array. Each bitline pair includes a first bitline coupled to the first grouping of rows and a second bitline coupled to the second grouping of rows of respective columns of the pixel array. Multiplexers are configured to select one of respective first or second bitlines of each bitline pair. A PDAF multiplexer is coupled to a PDAF select signal and the second PDAF circuit through a respective bitline pair. The remaining multiplexers are coupled to a select signal and are coupled to remaining bitline pairs.

    Bias circuit for use with divided bit lines

    公开(公告)号:US10819936B2

    公开(公告)日:2020-10-27

    申请号:US16275092

    申请日:2019-02-13

    Abstract: An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.

    Comparator for double ramp analog to digital converter

    公开(公告)号:US10326958B2

    公开(公告)日:2019-06-18

    申请号:US16035363

    申请日:2018-07-13

    Abstract: Apparatuses and method for an image sensor with increased analog to digital conversion range and reduced noise are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to auto-zero a reference voltage input of the comparator, adjusting an auto-zero offset voltage of a ramp voltage provided to the reference voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to auto-zero a bitline input of the comparator.

    Comparator for double ramp analog to digital converter

    公开(公告)号:US10079990B2

    公开(公告)日:2018-09-18

    申请号:US15277648

    申请日:2016-09-27

    CPC classification number: H04N5/378 H03K5/2481

    Abstract: Apparatuses and method for an image sensor with increased analog to digital conversion range and reduced noise are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to auto-zero a reference voltage input of the comparator, adjusting an auto-zero offset voltage of a ramp voltage provided to the reference voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to auto-zero a bitline input of the comparator.

    Feedback capacitor formed by bonding-via in pixel level bond

    公开(公告)号:US09859312B1

    公开(公告)日:2018-01-02

    申请号:US15427928

    申请日:2017-02-08

    Abstract: An image sensor includes a photodiode disposed in a first semiconductor material, and the photodiode is positioned to absorb image light through the backside of the first semiconductor material. A first floating diffusion is disposed proximate to the photodiode and coupled to receive image charge from the photodiode in response to a transfer signal applied to a transfer gate disposed between the photodiode and the first floating diffusion. A second semiconductor material, including a second floating diffusion, is disposed proximate to the frontside of the first semiconductor material. A dielectric material is disposed between the first semiconductor material and the second semiconductor material, and includes a first bonding via extending from the first floating diffusion to the second floating diffusion, a second bonding via disposed laterally proximate to the first bonding via, and a third bonding via disposed laterally proximate to the first bonding via.

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