公开(公告)号：US20140049329A1

公开(公告)日：2014-02-20

申请号：US13586033

申请日：2012-08-15

申请人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

发明人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

IPC分类号： H03L7/099

CPC分类号： H03K3/0322 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099

摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

摘要翻译： 本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。 在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。 基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。 例如，生成CP信号以分别控制第一CP和第二CP。 在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。 以这种方式，提供无分频PLL，从而减轻PLL功耗。

公开(公告)号：US08476972B2

公开(公告)日：2013-07-02

申请号：US12813620

申请日：2010-06-11

申请人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： G06G7/12 ,  G06G7/26

CPC分类号： G04F10/005

摘要： A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

摘要翻译： 时间放大器电路具有第一和第二反相器以及第一和第二下拉通路。 每个反相器包括第一NMOS晶体管和第一PMOS晶体管。 第一NMOS晶体管的源极直接或通过具有耦合到相应输入节点的栅极的第一附加NMOS晶体管耦合到接地节点。 第一和第二反相器分别耦合到第一和第二输入节点以及第一和第二输出节点。 第一下拉路径从第一输出节点到接地节点，并且响应于第一输入信号而使第二输出信号为高。 第二下拉路径从第二输出节点到地，并且响应于第二输入信号并且第一输出信号为高而使能。

公开(公告)号：US08324658B2

公开(公告)日：2012-12-04

申请号：US12759743

申请日：2010-04-14

申请人： Ming-Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Ming-Hsiang Song

发明人： Ming-Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Ming-Hsiang Song

IPC分类号： H01L29/73

CPC分类号： H01L29/73

摘要： An electrostatic discharge (ESD) protection circuit structure includes a dual directional silicon controlled rectifier (SCR) formed in a substrate. The SCR includes first and second P-wells laterally interposed by an N-well. A deep N-well is disposed underneath the P-wells and the N-well. First and second N-type regions are disposed in the first and second P-wells, respectively, and are coupled to a pair of pads. First and second P-type regions are disposed in the first and second P-wells, respectively, are coupled to the pads, and are disposed closer to the N-well than the first and second N-type regions, respectively.

摘要翻译： 静电放电（ESD）保护电路结构包括形成在衬底中的双向可控硅整流器（SCR）。 SCR包括由N阱横向插入的第一和第二P阱。 深井N井位于P井和N井的下面。 第一和第二N型区域分别设置在第一和第二P阱中，并且耦合到一对焊盘。 第一和第二P型区域分别设置在第一和第二P阱中，分别耦合到焊盘，并且分别设置成比第一和第二N型区域更靠近N阱。

公开(公告)号：US20120286836A1

公开(公告)日：2012-11-15

申请号：US13103571

申请日：2011-05-09

申请人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H03K3/84

CPC分类号： G01R31/2824

摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

摘要翻译： 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

公开(公告)号：US20100090738A1

公开(公告)日：2010-04-15

申请号：US12250224

申请日：2008-10-13

申请人： Wei-Pin Changchein ,  Shu Yi Ying ,  Fu-Lung Hsueh

发明人： Wei-Pin Changchein ,  Shu Yi Ying ,  Fu-Lung Hsueh

IPC分类号： H03K5/12

CPC分类号： H03K19/00323 ,  G06F1/10

摘要： Circuit and methods for automatic clock skew compensation in circuits having two power domains. When one of the power domains is operated with a lowered supply voltage, lowering the supply voltage tends to slow the clock pulse and produces clock skew. Circuitry is provided for selectively delaying the clock pulse in one of the power domains to reduce the clock skew by comparing the clock pulses, and then automatically delaying the clock pulse in one of the domains by a delay determined to minimize the skew. A method is provided where the clock skew between two clock pulses is determined and the delay needed in one of the clock pulses to reduce the skew is determined by sampling the clock skew using a plurality of delays at multiples of a minimum delay, and then automatically delaying the one clock pulse by selecting an appropriate delay. The method may be iterated.

摘要翻译： 具有两个电源域的电路中自动时钟偏移补偿的电路和方法。 当其中一个电源域以较低的电源电压工作时，降低电源电压会降低时钟脉冲并产生时钟偏移。 提供电路，用于选择性地延迟其中一个功率域中的时钟脉冲，以通过比较时钟脉冲来减小时钟偏移，然后自动延迟其中一个域中的时钟脉冲延迟确定的最小化偏差的延迟。 提供了一种方法，其中确定了两个时钟脉冲之间的时钟偏移，并且通过使用多个延迟以最小延迟的倍数对时钟偏差进行采样来确定在其中一个时钟脉冲中减少偏斜所需的延迟，然后自动地 通过选择适当的延迟来延迟一个时钟脉冲。 可以重复该方法。

公开(公告)号：US20060114140A1

公开(公告)日：2006-06-01

申请号：US10998389

申请日：2004-11-29

申请人： Fu-Lung Hsueh

发明人： Fu-Lung Hsueh

IPC分类号： H03M1/12

CPC分类号： H03M1/146

摘要： This invention discloses a method for converting an analog signal to a digital signal as the following steps. A reference voltage range is divided into a plurality of reference levels. The analog signal is compared with the reference levels to generate first conversion bits. A reference voltage sub-range defined by a first value and a second value of the reference level is selected, wherein the voltage level of the analog signal is higher than the first value and lower than the second value. The reference voltage sub-range is divided into a plurality of reference sub-levels. The analog signal is compared with the reference sub-levels to generate second conversion bits. The digital signal representing the analog signal is generated based on the first-conversion bits and the second conversion bits.

摘要翻译： 本发明公开了一种将模拟信号转换为数字信号的方法，如下步骤。 参考电压范围被分成多个参考电平。 将模拟信号与参考电平进行比较以产生第一转换位。 选择由参考电平的第一值和第二值定义的参考电压子范围，其中模拟信号的电压电平高于第一值并低于第二值。 参考电压子范围被分成多个参考子电平。 将模拟信号与参考子电平进行比较以产生第二转换位。 代表模拟信号的数字信号是基于第一转换位和第二转换位产生的。

公开(公告)号：US06608580B2

公开(公告)日：2003-08-19

申请号：US09784792

申请日：2001-02-15

申请人： Fu-Lung Hsueh

发明人： Fu-Lung Hsueh

IPC分类号： H03M112

CPC分类号： H03M1/0682 ,  H03M1/46

摘要： A method and system for converting a plurality of input signals being indicative of a signal to be converted to a digital output including: setting a plurality of codes each being indicative of a corresponding reference level; and, for each one of the codes, converting the one code to a first analog signal, and summing the first analog signal with a first of the input signals to provide a first summed signal; complementing the one code to provide a complemented code, converting the complemented code to a second analog signal; summing the second analog signal with a second of the input signals to provide a second summed signal corresponding to the first summed signal. The corresponding first and second summed signals are compared to provide a comparison signal. At least a portion of the digital output is set according to the comparison signal.

公开(公告)号：US06229506B1

公开(公告)日：2001-05-08

申请号：US09064696

申请日：1998-04-22

申请人： Robin Mark Adrian Dawson ,  Michael Gillis Kane ,  James Ya-Kong Hsu ,  Fu-Lung Hsueh ,  Alfred Charles Ipri ,  Roger Green Stewart

发明人： Robin Mark Adrian Dawson ,  Michael Gillis Kane ,  James Ya-Kong Hsu ,  Fu-Lung Hsueh ,  Alfred Charles Ipri ,  Roger Green Stewart

IPC分类号： G09G332

CPC分类号： G09G3/3233 ,  G09G3/325 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2320/02 ,  G09G2320/043

摘要： A LED pixel structure that reduces current nonuniformities and threshold voltage variations in a “drive transistor”of the pixel structure is disclosed. The LED pixel structure incorporates a current source for loading data into the pixel via a data line. Alternatively, an auto zero voltage is determined for the drive transistor prior to the loading of data.

摘要翻译： 公开了一种降低像素结构的“驱动晶体管”中的电流不均匀性和阈值电压变化的LED像素结构。 LED像素结构包含用于经由数据线将数据加载到像素中的电流源。 或者，在加载数据之前，确定驱动晶体管的自动零电压。

公开(公告)号：US06104041A

公开(公告)日：2000-08-15

申请号：US87570

申请日：1998-05-29

申请人： Fu-Lung Hsueh ,  Alfred Charles Ipri

发明人： Fu-Lung Hsueh ,  Alfred Charles Ipri

IPC分类号： H01L29/04

CPC分类号： H01L27/12 ,  H01L29/404 ,  H01L29/78624

摘要： In an active matrix electroluminescent display, a pixel containing a electroluminescent cell and the switching electronics for the electroluminescent cell where said switching electronics contains two transistors, a low voltage MOS transistor and a high voltage MOS transistor. A low voltage transistor is controlled by signals on a data and a select line. When activated, the low voltage transistor activates the high voltage transistor by charging the gate of the high voltage transistor. The gate charge is stored between the gate electrode of the high voltage transistor and an electric field shield forming a pixel signal capacitor. The pixel signal capacitor is positioned within the layout of the pixel a distance from the drain of the high voltage MOS transistor.

摘要翻译： 在有源矩阵电致发光显示器中，包含电致发光单元的像素和用于电致发光单元的开关电子器件，其中所述开关电子器件包含两个晶体管，低电压MOS晶体管和高压MOS晶体管。 低电压晶体管由数据和选择线上的信号控制。 当激活时，低压晶体管通过对高电压晶体管的栅极充电来激活高电压晶体管。 栅极电荷存储在高压晶体管的栅电极和形成像素信号电容器的电场屏蔽之间。 像素信号电容器位于与高压MOS晶体管的漏极相距一定距离的像素的布局内。

公开(公告)号：US5291198A

公开(公告)日：1994-03-01

申请号：US887761

申请日：1992-05-29

申请人： Andrew G. F. Dingwall ,  Fu-Lung Hsueh

发明人： Andrew G. F. Dingwall ,  Fu-Lung Hsueh

IPC分类号： H03M1/20 ,  H03M1/36

CPC分类号： H03M1/204 ,  H03M1/205 ,  H03M1/365

摘要： A flash-type analog-to-digital converter (ADC) uses only 2.sup.n-m comparators coupled to the analog input line to generate a n-bit digital output signal. Each pair of these actual comparators are coupled, in parallel, to 2.sup.m pseudocomparators which provide values representing comparisons of the input signal value to respective reference values between the reference values used by the actual comparators. The output signals of each pair of actual comparators are combined in respectively different proportions at each of the pseudocomparators. In this manner, the output signals of the actual comparators are averaged to produce the interstitial comparison values. In one embodiment of the invention, the ADC is implemented in BiCMOS technology with a bipolar differential input stage and a CMOS latching comparator. Signals are distributed from the actual comparators to the pseudocomparators via a pair of resistive ladder networks. In other embodiments of the invention the ADC is implemented in CMOS technology and the pseudocomparators use ratioed transistor widths and ratioed capacitors to proportionally divide the output signals of the actual comparators in order to generate the interstitial output values. A final embodiment of the invention combines two averaging flash ADCs to form a novel subranging ADC.

摘要翻译： 闪存型模数转换器（ADC）仅使用耦合到模拟输入线的2n-m个比较器来产生n位数字输出信号。 这些实际比较器中的每一对并联耦合到2m伪同步器，其提供表示将输入信号值与实际比较器使用的参考值之间的相应参考值进行比较的值。 每对实际比较器的输出信号在每个伪同步器上以不同的比例组合。 以这种方式，实际比较器的输出信号被平均以产生间隙比较值。 在本发明的一个实施例中，ADC采用BiCMOS技术实现，具有双极性差分输入级和CMOS锁存比较器。 信号通过一对电阻梯形网络从实际的比较器分布到伪同步器。 在本发明的其他实施例中，ADC以CMOS技术实现，并且伪同步器使用比例的晶体管宽度和比例的电容器来成比例地划分实际比较器的输出信号，以便产生间隙输出值。 本发明的最终实施例组合了两个平均闪光ADC，以形成新型的Subranging ADC。