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    Insertion-override counter to support multiple memory refresh rates
    51.
    发明授权
    Insertion-override counter to support multiple memory refresh rates 有权
    插入覆盖计数器，以支持多个内存刷新率

    公开(公告)号：US09368187B2

    公开(公告)日：2016-06-14

    申请号：US14149543

    申请日：2014-01-07

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jung Pill Kim

    IPC: G11C7/00 ,  G11C11/406

    CPC classification number: G11C11/40618 ,  G11C11/40611 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

    Abstract: A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based on an actual weak page address. The method also includes performing inserted refresh operations at the determined positions to coordinate distribution of the inserted refresh operations among the regularly scheduled refresh operations.

    Abstract translation: 存储器刷新方法包括确定在存储器块的正常行的规则调度的刷新操作中插入存储器块的弱行的刷新操作的位置。 刷新操作以基本恒定的刷新率发生。 要插入的位置基于实际的弱页面地址。 该方法还包括在所确定的位置处执行插入的刷新操作，以协调在规则排列的刷新操作之间插入的刷新操作的分布。

    Kernel masking of DRAM defects
    53.
    发明授权
    Kernel masking of DRAM defects 有权
    DRAM缺陷的内核屏蔽

    公开(公告)号：US09299457B2

    公开(公告)日：2016-03-29

    申请号：US14187279

    申请日：2014-02-23

    Applicant: QUALCOMM INCORPORATED

    Inventor： Dexter T. Chun ,  Yanru Li ,  Xiangyu Dong ,  Jungwon Suh ,  Jung Pill Kim ,  Deepti Vijayalakshmi Sriramagiri

    IPC: G11C29/00 ,  G11C29/44 ,  G06F11/10 ,  G06F11/20 ,  G06F12/02

    CPC classification number: G11C29/44 ,  G06F11/1048 ,  G06F11/1076 ,  G06F11/2053 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C2029/4402

    Abstract: Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

    Abstract translation: 公开了用于内核屏蔽动态随机存取存储器（DRAM）缺陷的系统，方法和计算机程序。 一种这样的方法包括：检测和校正与动态随机存取存储器（DRAM）中的物理地址相关的单位错误; 从DRAM接收与物理地址相关联的错误数据; 将接收到的错误数据存储在位于非易失性存储器中的故障地址表中; 并且如果与物理地址相关联的错误的数量超过错误计数阈值，则退出对应于物理地址的内核页面。

    Method and apparatus for multiple-bit DRAM error recovery
    55.
    发明授权
    Method and apparatus for multiple-bit DRAM error recovery 有权
    用于多位DRAM错误恢复的方法和装置

    公开(公告)号：US09274888B2

    公开(公告)日：2016-03-01

    申请号：US14081645

    申请日：2013-11-15

    Applicant: QUALCOMM Incorporated

    Inventor： Dexter Tamio Chun ,  Jung Pill Kim ,  Hyunsuk Shin ,  Jungwon Suh

    IPC: G11C29/00 ,  G06F11/10 ,  G06F11/14

    CPC classification number: G06F11/1072 ,  G06F11/1048 ,  G06F11/14 ,  G11C29/765

    Abstract: A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.

    Abstract translation: 当读取页面时，用于替换存储在系统存储器中的页面的系统产生多位错误。 在读取检测到多位错误的系统存储器中的页面时，闪存中的备份数据被加载到系统存储器中的冗余页面中，并且配置重新映射器，以便将来对页面的访问被重定向到 冗余页面。

    Memory device having a local current sink
    56.
    发明授权
    Memory device having a local current sink 有权
    具有局部电流吸收器的存储器件

    公开(公告)号：US09196341B2

    公开(公告)日：2015-11-24

    申请号：US14246169

    申请日：2014-04-07

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Hari Rao

    IPC: G11C11/00 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  G06F17/50

    CPC classification number: G11C11/1675 ,  G06F17/5068 ,  G11C11/1659 ,  G11C11/2255 ,  G11C11/2297 ,  G11C29/08 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    Abstract: A memory device having a local current sink is disclosed. In a particular embodiment, an electronic device is disclosed. The electronic device includes one or more write drivers. The electronic device includes at least one Magnetic Tunnel Junction (MTJ) coupled to a bit line and coupled to a source line. The electronic device also includes a current sink circuit comprising a single transistor, the single transistor coupled to the bit line and to the source line.

    Abstract translation: 公开了一种具有局部电流吸收器的存储器件。 在特定实施例中，公开了一种电子设备。 电子设备包括一个或多个写入驱动器。 电子设备包括耦合到位线并耦合到源极线的至少一个磁隧道结（MTJ）。 电子设备还包括电流吸收电路，其包括单个晶体管，单个晶体管耦合到位线和源极线。

    Sense amplifier offset voltage reduction
    57.
    发明授权
    Sense amplifier offset voltage reduction 有权
    感应放大器失调电压降低

    公开(公告)号：US09140747B2

    公开(公告)日：2015-09-22

    申请号：US13947144

    申请日：2013-07-22

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Daeik D. Kim

    IPC: G11C7/00 ,  G01R31/28 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46 ,  G11C16/28 ,  G11C29/02

    CPC classification number: G01R31/2851 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46

    Abstract: A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.

    Abstract translation: 电路包括响应于存储测试码的多个锁存器的多个晶体管。 电路还包括耦合到数据单元并耦合到读出放大器的第一位线。 电路还包括耦合到参考单元并耦合到读出放大器的第二位线。 来自一组多个晶体管的电流经由第一位线被施加到数据单元。 基于测试代码来确定多个晶体管的集合。 电路还包括耦合到第一位线和第二位线的测试模式参考电路。

    Write pulse width scheme in a resistive memory
    58.
    发明授权
    Write pulse width scheme in a resistive memory 有权
    在电阻性存储器中写入脉冲宽度方案

    公开(公告)号：US09135975B2

    公开(公告)日：2015-09-15

    申请号：US14064959

    申请日：2013-10-28

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

    IPC: G11C11/16 ,  G11C29/54 ,  G11C13/00 ,  G11C29/02 ,  G11C29/24

    CPC classification number: G11C11/1675 ,  G11C11/1677 ,  G11C13/0002 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C29/24 ,  G11C2013/0083 ,  G11C2013/0092

    Abstract: A resistive memory array includes a controller, a test reset driver coupled to the controller, a test write driver also coupled to the controller, and a test read sense amplifier also coupled to the controller. The resistive memory array also includes a set of test resistive memory elements representing a resistive memory macro. The test resistive memory elements are coupled to the test reset driver, the test write driver and the test read sense amplifier. A change in the state of one of the test resistive memory elements represents a change in the state of a set of corresponding elements in the resistive memory macro.

    Abstract translation: 电阻性存储器阵列包括控制器，耦合到控制器的测试复位驱动器，还耦合到控制器的测试写入驱动器，以及还耦合到控制器的测试读取读出放大器。 电阻存储器阵列还包括表示电阻存储器宏的一组测试电阻存储器元件。 测试电阻存储元件耦合到测试复位驱动器，测试写驱动器和测试读读放大器。 一个测试电阻存储器元件的状态的变化表示电阻存储器宏中一组相应元件的状态的变化。

    Memory cell array with reserved sector for storing configuration information
    60.
    发明授权
    Memory cell array with reserved sector for storing configuration information 有权
    具有保留扇区的存储单元阵列用于存储配置信息

    公开(公告)号：US08913450B2

    公开(公告)日：2014-12-16

    申请号：US13680361

    申请日：2012-11-19

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim

    IPC: G11C7/00 ,  G11C7/20 ,  G11C16/20 ,  G11C29/00 ,  G11C29/44

    CPC classification number: G11C7/20 ,  G11C16/20 ,  G11C29/44 ,  G11C29/789 ,  G11C2029/4402

    Abstract: A memory device is provided including a cell array and a volatile storage device. The cell array may include a plurality of word lines, a plurality of bit lines, wherein a selection of a word line and bit line defines a memory cell address, and a non-volatile reserved word line for storing configuration information for the cell array. The volatile storage device is coupled to the cell array. The configuration information from the non-volatile reserved word line is copied to the volatile storage device upon power-up or initialization of the memory device.

    Abstract translation: 提供了包括单元阵列和易失性存储装置的存储装置。 单元阵列可以包括多个字线，多个位线，其中字线和位线的选择定义存储器单元地址，以及用于存储单元阵列的配置信息的非易失性保留字线。 易失性存储设备耦合到单元阵列。 来自非易失性保留字线的配置信息在上电或初始化存储器件时被复制到易失性存储设备。

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