公开(公告)号：US09337997B2

公开(公告)日：2016-05-10

申请号：US14199898

申请日：2014-03-06

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H04L27/00 ,  H04L7/033 ,  H04L7/027 ,  H04L7/00 ,  H04L25/49 ,  H04L25/493 ,  H03K5/1252 ,  H03K5/1534 ,  H04L25/14 ,  H04L25/02

CPC classification number: H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

Abstract translation: 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换编号从一组顺序符号编号转换成顺序符号。 顺序符号号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播扩展到多条n线，其中时钟信号被有效地嵌入在原始符号的传输中，因为从转换数转换为顺序符号，保证没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零的差分电压。

公开(公告)号：US20150301980A1

公开(公告)日：2015-10-22

申请号：US14682846

申请日：2015-04-09

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/42

CPC classification number: G06F13/4295 ,  G06F13/4282 ,  G06F13/4291

Abstract: System, methods and apparatus are described that offer improved performance of a camera control interface (CCIe) bus. A method of data communications includes transmitting a first synchronization code on a serial bus, establishing synchronization with a first device coupled to the serial bus in response to the first synchronization code, communicating with the first device over the serial bus in accordance with a first protocol, after establishing synchronization with the first device, transmitting a first unsynchronization code on the serial bus, where the unsynchronization code is configured to cause a loss of synchronization with the first device, transmitting a second synchronization code on the serial bus, establishing synchronization with a second device coupled to the serial bus in response to the second synchronization code, and communicating with the second device over the serial bus in accordance with a second protocol, after establishing synchronization with the second device.

Abstract translation: 描述了提供相机控制接口（CCIe）总线的改进的性能的系统，方法和装置。 一种数据通信方法包括：在串行总线上发送第一同步码，响应于第一同步码与耦合到串行总线的第一设备建立同步，根据第一协议通过串行总线与第一设备进行通信 在与所述第一设备建立同步之后，在所述串行总线上发送第一非同步代码，其中所述非同步代码被配置为引起与所述第一设备的同步丢失，在所述串行总线上发送第二同步代码，建立与所述串行总线的同步 第二设备响应于第二同步代码耦合到串行总线，并且在与第二设备建立同步之后，根据第二协议通过串行总线与第二设备通信。

公开(公告)号：US20150295701A1

公开(公告)日：2015-10-15

申请号：US14250119

申请日：2014-04-10

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L7/00 ,  H04L25/02 ,  H04L7/033

CPC classification number: H04L7/0008 ,  H04L7/0066 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/0272

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multi-lane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link.

Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 使用从在多通道接口的第一通道上发送的第一符号序列提取的时钟来接收和解码第一符号序列，并且接收和解码在多通道接口的第二通道上发送的数据和/ 车道界面 时钟信号可以从第一符号序列中的连续符号对之间的N条线路的信令状态的转换导出。 第一条车道可以使用N！ 编码和第二个通道可能是串行或N！ 链接。

公开(公告)号：US20150286608A1

公开(公告)日：2015-10-08

申请号：US14700860

申请日：2015-04-30

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L12/6418

Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.

Abstract translation: 描述了提供内部集成电路（I2C）总线的改进性能的系统，方法和装置。 主数据可以根据I2C总线协议在第一信令中编码，并且第一信令可以与第二信令组合以获得用于在I2C总线上传输的组合信令。 次级数据可以在第二信令中被编码，其中组合信令与I2C总线协议保持兼容。 第二信令可以调制第一信令中的至少一个信号的电压电平。 第二个信令可以对I2C总线上发送的时钟信号进行脉宽调制。 第二信令可以修改在I2C总线上发送的字节之间的起始条件。 第二信令可以将多个短脉冲添加到在第一信令中发送的时钟信号。

公开(公告)号：US20150199295A1

公开(公告)日：2015-07-16

申请号：US14616572

申请日：2015-02-06

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4234 ,  G06F1/12 ,  G06F13/364 ,  H04L7/0037

Abstract: Master and slave devices may be coupled to a control data bus. A method includes controlling data transmissions over a bus using a master device. A clock signal is provided by the master device on a clock line (SCL) of a serial bus, a receive clock generated from transitions on the SCL line when a slave device is transmitting data on the SDA line, is calibrated using a delay based on a duration of time measured between an edge of the clock signal provided on the SCL line and at least one transition produced on the SDA line by a slave device in response to the edge of the clock signal. Data, including double data rate data, may be reliably received using the calibrated receive clock.

Abstract translation: 主设备和从设备可以耦合到控制数据总线。 一种方法包括使用主设备控制总线上的数据传输。 主器件在串行总线的时钟线（SCL）上提供时钟信号，当从器件在SDA线上传输数据时，从SCL线上的转换产生的接收时钟使用基于 在SCL线上提供的时钟信号的边沿与响应于时钟信号的边缘的从设备在SDA线上产生的至少一个转换之间所测量的持续时间。 可以使用校准的接收时钟可靠地接收包括双倍数据速率数据的数据。

公开(公告)号：US20150168991A1

公开(公告)日：2015-06-18

申请号：US14572680

申请日：2014-12-16

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F1/04 ,  G06F13/42

CPC classification number: G06F1/04 ,  G06F1/3237 ,  G06F1/324 ,  G06F13/00 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4291 ,  G06F13/4295 ,  H04L7/0087 ,  H04L7/027

Abstract: Methods, apparatus, and computer program products are described, which provide a mechanism that enables data to be written into registers of a slave device without a free-running clock, while facilitating an efficient sleep and wakeup mechanism for slave devices. A receiver device may receive a plurality of symbols over a shared bus, extract a receive clock signal embedded in symbol-to-symbol transitions of the plurality of symbols, convert the plurality of symbols into a transition number, convert the transition number into data bits, and store at least a portion of the data bits into one or more registers using only the receive clock signal. The receiver device may start a down counter upon detection of a first cycle of the clock signal, trigger a marker when the down counter reaches a pre-defined value, and use the marker to store at least a portion of the data bits into registers.

Abstract translation: 描述了方法，装置和计算机程序产品，其提供了使得数据能够被写入到从设备的寄存器中而没有自由运行的时钟的机制，同时促进用于从设备的有效的睡眠和唤醒机制。 接收机设备可以通过共享总线接收多个符号，提取嵌入在多个符号的符号到符号转换中的接收时钟信号，将多个符号转换成转换号码，将转换号码转换成数据位 并且仅使用接收时钟信号将至少一部分数据比特存储到一个或多个寄存器中。 接收机设备可以在检测到时钟信号的第一周期时启动递减计数器，当递减计数器达到预定义值时触发标记，并使用标记将数据位的至少一部分存储到寄存器中。

公开(公告)号：US20150100712A1

公开(公告)日：2015-04-09

申请号：US14507179

申请日：2014-10-06

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4004 ,  G06F13/28 ,  G06F13/36 ,  G06F13/42

Abstract: In a shared bus where communications are managed by a master device, direct slave device to slave device (S2S) communications is implemented. A first slave device wanting to communicate with a second slave device may make a S2S communication request to the master device. The request may include a requested number of words that the first slave device wishes to send over the shared bus. The master device may have a current word limit which may vary based upon operating parameters. The master device may deny the request if the requested number of words is greater than the current word limit or if it does not support S2S communications. Denial of the request may also be for other reasons, like activity over the shared bus. If the master device grants the request, the slave device may send the requested number of words to another slave device over the shared bus.

Abstract translation: 在由主设备管理通信的共享总线中，实现直接从设备到从设备（S2S）通信。 希望与第二从设备通信的第一从设备可以向主设备发送S2S通信请求。 请求可以包括第一从设备希望通过共享总线发送的所请求的字数。 主设备可以具有当前字限制，其可以基于操作参数而变化。 如果所请求的字数大于当前字限制，或者如果不支持S2S通信，则主设备可以拒绝该请求。 拒绝请求也可能是由于其他原因，如共享总线上的活动。 如果主设备授权请求，则从设备可以通过共享总线将所请求的字数发送到另一个从设备。

公开(公告)号：US20150098537A1

公开(公告)日：2015-04-09

申请号：US14491884

申请日：2014-09-19

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L7/00 ,  H04L7/04

CPC classification number: H04L7/0087 ,  H04L7/0008 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/04 ,  H04L25/14

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 可以在数据通信链路的数据通道上承载的信号中或在数据通信链路的定时通道上承载的信号中检测到第一转换，并且可以基于第一转换在接收器时钟信号上产生边沿。 可以使用接收机时钟信号从数据通道捕获数据。 定时通道可以携带时钟信号，选通信号或提供定时信息的另一个信号。 当在连续数据周期之间的边界处的多个数据通道中的任一个上没有发生状态转换时，选通信号可能在信令状态之间转变。

公开(公告)号：US20140270026A1

公开(公告)日：2014-09-18

申请号：US14205242

申请日：2014-03-11

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: H04L7/027

CPC classification number: H04L7/027 ,  G06F13/4072 ,  G06F13/4295 ,  H04L25/00 ,  H04L25/14

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 数据比特序列被转换成M个转换号码，然后转换成符号序列。 通过N线接收符号序列。 可以有效地将时钟信号嵌入到符号序列的传输中。 符号序列中的每一个可以基于M个转移号码中的一个和符号序列中的前一个的值来选择。

公开(公告)号：US09904637B2

公开(公告)日：2018-02-27

申请号：US14949534

申请日：2015-11-23

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/24 ,  G06F13/42 ,  G06F1/14 ,  G06F13/366 ,  G06F13/362 ,  G06F13/40

CPC classification number: G06F13/24 ,  G06F1/14 ,  G06F13/3625 ,  G06F13/366 ,  G06F13/4004 ,  G06F13/4282

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A method performed by a slave device coupled to a serial bus includes detecting an event related to a function of the slave device, initiating a first counter in the slave device, asserting an in-band interrupt request by driving at least one signal on the serial bus, and transmitting content of the first counter to a bus master coupled to the serial bus during an interrupt handling procedure. The first counter may count cycles of a clock used by the slave device or occurrences of a signaling state or condition on the serial bus. The content of the first counter may be used to determine a time stamp for the event.