公开(公告)号：US20190139583A1

公开(公告)日：2019-05-09

申请号：US16148491

申请日：2018-10-01

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John W. Poulton

IPC: G11C5/14 ,  H04L1/20 ,  H04L25/02 ,  H04L25/08 ,  G06F11/07 ,  G06F13/40

CPC classification number: G11C5/144 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0793 ,  G06F13/4072 ,  G11C5/145 ,  H04L1/203 ,  H04L25/0264 ,  H04L25/08

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

公开(公告)号：US10146608B2

公开(公告)日：2018-12-04

申请号：US15090399

申请日：2016-04-04

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

IPC: G06F11/07 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US10108488B2

公开(公告)日：2018-10-23

申请号：US15254431

申请日：2016-09-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/00 ,  H03M13/19 ,  G06F11/08

Abstract: A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. Individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.

公开(公告)号：US20180293130A1

公开(公告)日：2018-10-11

申请号：US15907210

申请日：2018-02-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/10 ,  G11C29/44 ,  G11C29/42 ,  G11C5/04 ,  G11C29/04

CPC classification number: G06F11/1048 ,  G11C5/04 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US09858216B2

公开(公告)日：2018-01-02

申请号：US15173932

申请日：2016-06-06

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ian Shaeffer

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093

CPC classification number: G06F13/1689 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0683 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  Y02D10/14

Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

公开(公告)号：US20170337144A1

公开(公告)日：2017-11-23

申请号：US15525379

申请日：2015-11-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Craig E. Hampel ,  Scott C. Best ,  John Yan

IPC: G06F13/16

CPC classification number: G06F13/1678 ,  G06F13/1673 ,  G06F13/1694

Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility, or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

公开(公告)号：US09741423B2

公开(公告)日：2017-08-22

申请号：US15259854

申请日：2016-09-08

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

IPC: G11C11/4076 ,  G11C11/4091

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

公开(公告)号：US20170102992A1

公开(公告)日：2017-04-13

申请号：US15254431

申请日：2016-09-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: G06F11/10 ,  H03M13/19

CPC classification number: G06F11/1048 ,  H03M13/1525 ,  H03M13/19 ,  H03M13/617

Abstract: A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. Individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.

公开(公告)号：US20170004099A1

公开(公告)日：2017-01-05

申请号：US15173932

申请日：2016-06-06

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ian Shaeffer

IPC: G06F13/16 ,  G11C11/4093 ,  G06F3/06 ,  G11C11/409 ,  G11C11/4076

CPC classification number: G06F13/1689 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0683 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  Y02D10/14

Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

Abstract translation: 存储器系统包括耦合到多个存储器件的存储器控​​制器。 每个存储器件包括产生内部参考信号的振荡器，该内部参考信号以存储器件内的物理器件结构的函数的频率振荡。 因此，内部参考信号的频率是器件特定的。 每个存储器件从其内部参考信号产生共享参考信号，并将共享参考信号传送到公共存储器控制器。 存储器控制器使用共享参考信号从每个存储器件恢复器件特定的频率信息，然后以与相应的内部参考信号兼容的频率与每个存储器件通信。

公开(公告)号：US09466353B2

公开(公告)日：2016-10-11

申请号：US14849425

申请日：2015-09-09

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

IPC: H04L7/00 ,  G11C11/4076 ,  G06F1/10 ,  G11C7/10 ,  G11C7/22 ,  H03L7/07 ,  H03L7/081 ,  H04L7/033 ,  G11C7/04

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.