公开(公告)号：US10811062B2

公开(公告)日：2020-10-20

申请号：US16528523

申请日：2019-07-31

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20190295604A1

公开(公告)日：2019-09-26

申请号：US16256887

申请日：2019-01-24

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/06 ,  H01L23/48 ,  H01L25/065 ,  H01L27/108 ,  G11C5/02

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US10378967B1

公开(公告)日：2019-08-13

申请号：US15794280

申请日：2017-10-26

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Frederick A. Ware

IPC: H03K19/0175 ,  G05F3/24 ,  G01K7/01 ,  G05F1/56

Abstract: During operation of an IC component within a first range of temperatures, a first bias voltage is applied to a first substrate region disposed adjacent a first plurality of transistors to effect a first threshold voltage for the first plurality of transistors. During operation of the IC component within a second range of temperatures that is distinct from and lower than the first range of temperatures, a second bias voltage is applied to the first substrate region to effect a second threshold voltage for the first plurality of transistors that is at least as low as the first threshold voltage.

公开(公告)号：US20190164588A1

公开(公告)日：2019-05-30

申请号：US16097579

申请日：2017-05-03

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Brent Steven Haukness ,  Kenneth L. Wright ,  Thomas Vogelsang

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/409 ,  G11C11/408

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

公开(公告)号：US10262750B2

公开(公告)日：2019-04-16

申请号：US15393634

申请日：2016-12-29

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  William Ng ,  Frederick A. Ware

IPC: G01R31/28 ,  G11C29/02 ,  H01L21/66 ,  H01L25/065 ,  G11C8/10 ,  G11C29/04 ,  G11C5/02 ,  G11C5/06

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

公开(公告)号：US10248358B2

公开(公告)日：2019-04-02

申请号：US15990211

申请日：2018-05-25

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G11C7/10 ,  G11C29/02 ,  G06F11/10 ,  G11C29/04

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US10199089B2

公开(公告)日：2019-02-05

申请号：US15876539

申请日：2018-01-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C8/00 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

公开(公告)号：US20180341432A1

公开(公告)日：2018-11-29

申请号：US15990211

申请日：2018-05-25

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G06F11/10 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2207/107

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US20180270432A1

公开(公告)日：2018-09-20

申请号：US15759963

申请日：2016-09-20

Applicant: Rambus Inc.

Inventor： Jay Endsley ,  Thomas Vogelsang ,  Craig M. Smith ,  Michael Guidash ,  Alexander C. Schneider

IPC: H04N5/378 ,  H04N5/355 ,  H04N5/235 ,  H04N5/353

CPC classification number: H04N5/378 ,  H04N5/2355 ,  H04N5/3532 ,  H04N5/35536 ,  H04N5/35554

Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.

公开(公告)号：US09983830B2

公开(公告)日：2018-05-29

申请号：US15022176

申请日：2014-09-23

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G11C7/10 ,  G11C29/02 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2207/107

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.