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公开(公告)号：US10770124B2
公开(公告)日：2020-09-08
申请号：US16222909
申请日：2018-12-17
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Lawrence Lai , Fan Ho , David A. Secker , Wayne S. Richardson , Akash Bansal , Brian S. Leibowitz , Kyung Suk Oh
Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
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公开(公告)号：US20200089270A1
公开(公告)日：2020-03-19
申请号：US16566287
申请日：2019-09-10
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
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公开(公告)号：US10331379B2
公开(公告)日：2019-06-25
申请号：US15486068
申请日：2017-04-12
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Craig E. Hampel , Wayne S. Richardson , Chad A. Bellows , Lawrence Lai
IPC: G06F3/06 , G11C7/10 , G11C7/22 , G11C8/06 , G11C11/4076 , G11C11/4097
Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.
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公开(公告)号：US20190180813A1
公开(公告)日：2019-06-13
申请号：US16276338
申请日：2019-02-14
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C11/406 , G11C11/4074 , G06F1/3234 , G11C29/02 , G11C7/02 , G11C11/4072 , G11C7/20
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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公开(公告)号：US20190139598A1
公开(公告)日：2019-05-09
申请号：US16235351
申请日：2018-12-28
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C11/406 , G11C11/4074 , G06F1/3234 , G11C29/02 , G11C7/02 , G11C11/4072 , G11C7/20
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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Patent Agency Ranking
公开(公告)号：US10262718B2
公开(公告)日：2019-04-16
申请号：US15855535
申请日：2017-12-27
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C8/00 , G11C11/406 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C29/02 , G06F1/3234 , G11C11/4074
Abstract: In one embodiment, a memory device includes a clock receiver to receive a clock signal and a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal. The plurality of clock frequencies include a first clock frequency and a second clock frequency. The memory device also includes a command interface to receive commands synchronously with respect to the clock signal. The command interface receives a command that instructs the DRAM device to change operation from the first clock frequency to the second clock frequency.
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公开(公告)号：US10192598B2
公开(公告)日：2019-01-29
申请号：US15623261
申请日：2017-06-14
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Lawrence Lai , Fan Ho , David A. Secker , Wayne S. Richardson , Akash Bansal , Brian S. Leibowitz , Kyung Suk Oh
Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
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公开(公告)号：US09652176B2
公开(公告)日：2017-05-16
申请号：US14449610
申请日：2014-08-01
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Craig E. Hampel , Wayne S. Richardson , Chad A. Bellows , Lawrence Lai
IPC: G06F3/06 , G11C8/06 , G11C11/4076 , G11C7/22 , G11C7/10 , G11C11/4097
CPC classification number: G06F3/0659 , G06F3/0613 , G06F3/0673 , G11C7/1006 , G11C7/1042 , G11C7/22 , G11C8/06 , G11C11/4076 , G11C11/4097
Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.
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公开(公告)号：US20160161977A1
公开(公告)日：2016-06-09
申请号：US14961077
申请日：2015-12-07
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
CPC classification number: G06F1/08 , G06F1/10 , G06F13/1673 , G06F13/1689 , H03L7/07 , H03L7/0814 , H03L7/0995 , H04L7/0008 , H04L7/0033 , H04L7/10 , Y02D10/14
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
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公开(公告)号：US09292223B2
公开(公告)日：2016-03-22
申请号：US13901014
申请日：2013-05-23
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Craig E. Hampel , Wayne S. Richardson , Chad A. Bellows , Lawrence Lai
IPC: G06F3/06 , G11C7/10 , G11C8/06 , G11C11/4076 , G11C11/4097 , G11C7/22
CPC classification number: G06F3/0659 , G06F3/0613 , G06F3/0673 , G11C7/1006 , G11C7/1042 , G11C7/22 , G11C8/06 , G11C11/4076 , G11C11/4097
Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.
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