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    Method of using a semiconductor chip package
    53.
    发明授权
    Method of using a semiconductor chip package 有权
    使用半导体芯片封装的方法

    公开(公告)号：US06682946B2

    公开(公告)日：2004-01-27

    申请号：US10119461

    申请日：2002-04-10

    申请人： Jerrold L. King ,  Leland R. Nevill

    发明人： Jerrold L. King ,  Leland R. Nevill

    IPC分类号： H01L2166

    CPC分类号： H05K3/303 ,  G01R31/2851 ,  G01R31/2884 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2203/0195 ,  Y02P70/613

    摘要： An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces equate to three substantially conical indentations on the chip package and three substantially conical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.

    摘要翻译： 改进的半导体芯片封装，能够在电气测试制造阶段与测试设备独立对齐。 通过将两个基本上一致的表面（一个在芯片封装上）和一个在对准装置上装配在一起，将半导体芯片封装直接连接到测试对准装置，实现独立对准。 配合表面被布置成仅可实现一个可配合的位置。 基本上一致的表面等同于芯片封装上的三个基本上圆锥形的凹口，以及从对准装置延伸的基本上一致的尺寸和深度的三个基本上圆锥形的突起或突起。 一旦安装，三个突起将半导体芯片悬挂在基本上水平的平面中，使得电测试接触（也基本上在水平面）可以容易地与从半导体芯片大致水平并共面延伸的导电引线接触。

    Semiconductor chip package with alignment structure
    54.
    发明授权
    Semiconductor chip package with alignment structure 有权
    半导体芯片封装

    公开(公告)号：US06670720B2

    公开(公告)日：2003-12-30

    申请号：US09799179

    申请日：2001-03-05

    申请人： Jerrold L. King ,  Leland R. Nevill

    发明人： Jerrold L. King ,  Leland R. Nevill

    IPC分类号： H01L2348

    CPC分类号： H05K3/303 ,  G01R31/2851 ,  G01R31/2884 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2203/0195 ,  Y02P70/613

    摘要： An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces can equate to three substantially conical indentations on the chip package and three substantially conical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.

    摘要翻译： 改进的半导体芯片封装，能够在电气测试制造阶段与测试设备独立对齐。 通过将两个基本上一致的表面（一个在芯片封装上）和一个在对准装置上装配在一起，将半导体芯片封装直接连接到测试对准装置，实现独立对准。 配合表面被布置成仅可实现一个可配合的位置。 基本上一致的表面可以等同于芯片封装上的三个基本上圆锥形的凹口，以及从对准装置延伸的基本上一致的尺寸和深度的三个基本上圆锥形的突起或突起。 一旦安装，三个突起将半导体芯片悬挂在基本上水平的平面中，使得电测试接触（也基本上在水平面）可以容易地与从半导体芯片大致水平并共面延伸的导电引线接触。

    Semiconductor chip package
    55.
    发明授权
    Semiconductor chip package 失效
    半导体芯片封装

    公开(公告)号：US06198172B1

    公开(公告)日：2001-03-06

    申请号：US09026584

    申请日：1997-02-20

    申请人： Jerrold L. King ,  Leland R. Nevill

    发明人： Jerrold L. King ,  Leland R. Nevill

    IPC分类号： H01L23544

    CPC分类号： H05K3/303 ,  G01R31/2851 ,  G01R31/2884 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2203/0195 ,  Y02P70/613

    摘要： An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces equate to three substantially conical indentations on the chip package and three substantially conical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.

    摘要翻译： 改进的半导体芯片封装，能够在电气测试制造阶段与测试设备独立对齐。 通过将两个基本上一致的表面（一个在芯片封装上）和一个在对准装置上装配在一起，将半导体芯片封装直接连接到测试对准装置，实现独立对准。 配合表面被布置成仅可实现一个可配合的位置。 基本上一致的表面等同于芯片封装上的三个基本上圆锥形的凹口，以及从对准装置延伸的基本上一致的尺寸和深度的三个基本上圆锥形的突起或突起。 一旦安装，三个突起将半导体芯片悬挂在基本上水平的平面中，使得电测试接触（也基本上在水平面）可以容易地与从半导体芯片大致水平并共面延伸的导电引线接触。

    Circuit and method for enabling a function in a multiple memory device module
    57.
    发明授权
    Circuit and method for enabling a function in a multiple memory device module 失效

    公开(公告)号：US5825697A

    公开(公告)日：1998-10-20

    申请号：US577840

    申请日：1995-12-22

    申请人： Gary R. Gilliam ,  Kevin G. Duesman ,  Leland R. Nevill

    发明人： Gary R. Gilliam ,  Kevin G. Duesman ,  Leland R. Nevill

    IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/80 ,  G11C29/808

    摘要： A memory device module in a package having externally accessible contacts includes multiple integrated memory circuits accessible to external circuitry exclusively through the contacts. An accessing circuit for each memory circuit accesses memory cells in the memory circuit for communication with the external circuitry. Each accessing circuit can be enabled to access redundant memory cells instead of inoperative memory cells by an enabling signal. An enabling circuit for each accessing circuit can output the enabling signal in response to receiving a unique set of input signals from external circuitry. Each unique set is selected with fuses in each enabling circuit, and includes row and column address strobe signals and a data signal. Upon receiving its unique set, one of the enabling circuits advantageously enables its associated accessing circuit to access redundant memory cells without the accessing circuits of the other memory circuits also being so enabled.