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    Single-piece molded module housing
    5.
    发明授权
    Single-piece molded module housing 失效
    单件模制模块外壳

    公开(公告)号：US06781848B2

    公开(公告)日：2004-08-24

    申请号：US10443347

    申请日：2003-05-22

    申请人： Warren M. Farnworth ,  Jerrold L. King

    发明人： Warren M. Farnworth ,  Jerrold L. King

    IPC分类号： H05K714

    CPC分类号： H01R12/83 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01087 ,  H05K1/141 ,  H05K3/284 ,  H05K3/301 ,  H01L2924/00014

    摘要： An adapter or housing for a module, such as a single in-line memory module (SIMM) or the like, and method of using the same are herein disclosed where the SIMM and attached housing fit a predetermined shape SIMM socket. The housing replaces SIMM board material that would otherwise be used to help secure the SIMM to a predetermined shape SIMM socket or connector. The configuration of the housing allows a SIMM or the like to be snapped or slid and secured into the housing. If desired, an adhesive, potting material and other bonding material can be used to secure the SIMM board to the housing and/or pot the SIMM within the housing.

    摘要翻译： 本文公开了用于模块的适配器或壳体，例如单个在线存储器模块（SIMM）等，以及其中SIMM和附接的壳体适合预定形状的SIMM插座的方法。 外壳代替SIMM板材料，否则将用于帮助将SIMM固定到预定形状的SIMM插座或连接器上。 壳体的构造允许SIMM等被卡扣或滑动并固定到壳体中。 如果需要，可以使用粘合剂，灌封材料和其它粘合材料来将SIMM板固定到壳体内和/或将壳体内的SIMM固定。

    Method of aligning and testing a semiconductor chip package
    8.
    发明授权
    Method of aligning and testing a semiconductor chip package 有权
    半导体芯片封装对准和测试方法

    公开(公告)号：US06420195B1

    公开(公告)日：2002-07-16

    申请号：US09190545

    申请日：1998-11-12

    申请人： Jerrold L. King ,  Leland R. Nevill

    发明人： Jerrold L. King ,  Leland R. Nevill

    IPC分类号： G01R3126

    CPC分类号： H05K3/303 ,  G01R31/2851 ,  G01R31/2884 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2203/0195 ,  Y02P70/613

    摘要： An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces equate to three substantially conical indentations on the chip package and three substantially hemispherical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.

    摘要翻译： 改进的半导体芯片封装，能够在电气测试制造阶段与测试设备独立对齐。 通过将两个基本上一致的表面（一个在芯片封装上）和一个在对准装置上装配在一起，将半导体芯片封装直接连接到测试对准装置，实现独立对准。 配合表面被布置成仅可实现一个可配合的位置。 基本上一致的表面等于芯片封装上的三个基本上圆锥形的凹陷，以及从对准装置延伸的基本上一致的尺寸和深度的三个基本上半球形的突起或突起。 一旦安装，三个突起将半导体芯片悬挂在基本上水平的平面中，使得电测试接触（也基本上在水平面）可以容易地与从半导体芯片大致水平并共面延伸的导电引线接触。

    Low profile multi-IC chip package connector
    9.
    发明授权
    Low profile multi-IC chip package connector 有权

    公开(公告)号：US06362519B1

    公开(公告)日：2002-03-26

    申请号：US09836067

    申请日：2001-04-17

    申请人： Walter L. Moden ,  Jerrold L. King ,  Jerry M. Brooks

    发明人： Walter L. Moden ,  Jerrold L. King ,  Jerry M. Brooks

    IPC分类号： H01L2302

    摘要： A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.