公开(公告)号：US07586163B2

公开(公告)日：2009-09-08

申请号：US11287192

申请日：2005-11-28

申请人： Koichi Kato ,  Daisuke Matsushita ,  Koichi Muraoka ,  Yasushi Nakasaki ,  Yuichiro Mitani ,  Nobutoshi Aoki

发明人： Koichi Kato ,  Daisuke Matsushita ,  Koichi Muraoka ,  Yasushi Nakasaki ,  Yuichiro Mitani ,  Nobutoshi Aoki

IPC分类号： H01L29/76

CPC分类号： H01L29/16 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/518

摘要： A semiconductor device includes a semiconductor substrate; an insulation film provided on the semiconductor substrate; and an electrode provided on the insulation film, and containing boron and a semiconductor material, wherein at least one element of the group V and carbon is introduced into an interface between the insulation film and the electrode.

摘要翻译： 半导体器件包括半导体衬底; 设置在所述半导体基板上的绝缘膜; 以及设置在所述绝缘膜上并且含有硼和半导体材料的电极，其中所述V族和碳族中的至少一种元素被引入到所述绝缘膜和所述电极之间的界面中。

公开(公告)号：US20090008727A1

公开(公告)日：2009-01-08

申请号：US12208730

申请日：2008-09-11

申请人： Takashi YAMAUCHI ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato ,  Nobutoshi Aoki ,  Kazuya Ohuchi

发明人： Takashi YAMAUCHI ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato ,  Nobutoshi Aoki ,  Kazuya Ohuchi

IPC分类号： H01L29/78

CPC分类号： H01L21/28537 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66143 ,  H01L29/66643 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/872 ,  H01L2029/7858

摘要： It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.

摘要翻译： 可以降低硅化镍膜与硅之间界面处的界面电阻。 半导体制造方法包括：在硅衬底上形成杂质区域，杂质被引入杂质区域; 沉积Ni层以覆盖杂质区域; 通过退火将杂质区的表面改变为NiSi2层; 在NiSi2层上形成Ni层; 并通过退火将NiSi2层硅化。

公开(公告)号：US20070141836A1

公开(公告)日：2007-06-21

申请号：US11530724

申请日：2006-09-11

申请人： Takashi Yamauchi ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato ,  Nobutoshi Aoki ,  Kazuya Ohuchi

发明人： Takashi Yamauchi ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato ,  Nobutoshi Aoki ,  Kazuya Ohuchi

IPC分类号： H01L21/4763

CPC分类号： H01L21/28537 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66143 ,  H01L29/66643 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/872 ,  H01L2029/7858

摘要： It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.

摘要翻译： 可以降低硅化镍膜与硅之间界面处的界面电阻。 半导体制造方法包括：在硅衬底上形成杂质区域，杂质被引入杂质区域; 沉积Ni层以覆盖杂质区域; 通过退火将杂质区的表面改变成NiSi 2层; 在NiSi 2层上形成Ni层; 并通过退火对NiSi 2层进行硅化。

公开(公告)号：US20060289905A1

公开(公告)日：2006-12-28

申请号：US11442352

申请日：2006-05-30

申请人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Nobutoshi Aoki ,  Masaki Kondo ,  Sanae Ito

发明人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Nobutoshi Aoki ,  Masaki Kondo ,  Sanae Ito

IPC分类号： H01L29/76

CPC分类号： H01L29/1037 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853

摘要： A semiconductor device comprising at least one FET formed on the semiconductor substrate, wherein the FET comprises a source region, a drain region, a channel region formed between the source and drain regions and including a plurality of projected epitaxial silicon regions arranged in a width direction of the channel region, each of the projected epitaxial silicon regions having a triangular ridge portion, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件，包括形成在所述半导体衬底上的至少一个FET，其中所述FET包括源极区，漏极区，形成在所述源极和漏极区之间的沟道区，并且包括沿宽度方向布置的多个投影外延硅区 的沟道区域，每个投影的外延硅区域具有三角形脊部分，形成在沟道区域上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。

公开(公告)号：US06980942B2

公开(公告)日：2005-12-27

申请号：US09812365

申请日：2001-03-20

申请人： Naoki Kusunoki ,  Nobutoshi Aoki ,  Hirotaka Amakawa

发明人： Naoki Kusunoki ,  Nobutoshi Aoki ,  Hirotaka Amakawa

IPC分类号： G06F17/10 ,  G06F17/50 ,  H01L21/00

CPC分类号： G06F17/5018

摘要： Plural boundary points are generated on a string on the surface of a material and a first length of a line segment between the boundary points is obtained. Then, the displacement of the boundary point according to a process model and the boundary point is moved by the displacement. A second length of the line segment between the boundary points after the boundary point is moved is found. When the second length is greater than a value obtained by multiplying the first length by a first factor exceeding 1, a new boundary point is added to the line segment whereas when the second length is smaller than a value obtained by multiplying the first length by a second factor less than 1, one of the boundary points of the line segment is eliminated.

摘要翻译： 在材料的表面上的弦上产生多个边界点，并且获得边界点之间的线段的第一长度。 然后，根据过程模型和边界点的边界点的位移由位移移动。 发现边界点移动后边界点之间的线段的第二长度。 当第二长度大于通过将第一长度乘以第一因子超过1而获得的值时，新的边界点被添加到线段，而当第二长度小于通过将第一长度乘以一个 第二个因子小于1，线段的边界点之一被消除。

公开(公告)号：US06930360B2

公开(公告)日：2005-08-16

申请号：US10609392

申请日：2003-07-01

申请人： Jun Yamauchi ,  Nobutoshi Aoki

发明人： Jun Yamauchi ,  Nobutoshi Aoki

IPC分类号： H01L21/24 ,  H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L21/425 ,  H01L27/148 ,  H01L29/12 ,  H01L29/772 ,  H01L29/78 ,  A01L29/72

CPC分类号： H01L29/6659 ,  H01L21/2652

摘要： A semiconductor device having a semiconductor layer, includes: a first impurity atom having a covalent bond radius larger than a minimum radius of a covalent bond of a semiconductor constituent atom of a semiconductor layer; and a second impurity atom having a covalent bond radius smaller than a maximum radius of the covalent bond of the semiconductor constituent atom; wherein the first and second impurity atoms are arranged in a nearest neighbor lattice site location and at least one of the first and second impurity atoms is electrically active.

摘要翻译： 具有半导体层的半导体器件包括：具有大于半导体层半导体构成原子的共价键的最小半径的共价键半径的第一杂质原子; 和具有小于半导体组成原子的共价键的最大半径的共价键半径的第二杂质原子; 其中所述第一和第二杂质原子布置在最近的相邻晶格位置位置，并且所述第一和第二杂质原子中的至少一个是电活性的。

公开(公告)号：US08575684B2

公开(公告)日：2013-11-05

申请号：US13364602

申请日：2012-02-02

申请人： Takashi Izumida ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L29/788 ,  H01L29/423

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11578 ,  H01L27/11582

摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

公开(公告)号：US20130049122A1

公开(公告)日：2013-02-28

申请号：US13534665

申请日：2012-06-27

申请人： Toshitaka MIYATA ,  Nobutoshi Aoki

发明人： Toshitaka MIYATA ,  Nobutoshi Aoki

IPC分类号： H01L29/78 ,  H01L21/283

CPC分类号： H01L29/4983 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/76802 ,  H01L21/76838 ,  H01L29/512 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7831

摘要： In one embodiment, a semiconductor device includes a substrate, and a gate insulator disposed on the substrate. The device further includes a gate electrode including a first electrode layer which is disposed on an upper surface of the gate insulator and has a first work function, and a second electrode layer which is continuously disposed on the upper surface of the gate insulator and an upper surface of the first electrode layer and has a second work function that is different from the first work function, and sidewall insulators disposed on side surfaces of the gate electrode. A height of the upper surface of the first electrode layer is lower than a height of upper surfaces of the sidewall insulators.

摘要翻译： 在一个实施例中，半导体器件包括衬底和设置在衬底上的栅极绝缘体。 该器件还包括栅电极，该栅极包括设置在栅极绝缘体的上表面上并具有第一功函数的第一电极层和连续地设置在栅绝缘体的上表面上的第二电极层， 具有与第一功函数不同的第二功函数，以及配置在栅极侧面的侧壁绝缘体。 第一电极层的上表面的高度低于侧壁绝缘子的上表面的高度。

公开(公告)号：US08258562B2

公开(公告)日：2012-09-04

申请号：US12470030

申请日：2009-05-21

申请人： Takashi Izumida ,  Takahisa Kanemura ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Takahisa Kanemura ,  Nobutoshi Aoki

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.

摘要翻译： 本发明实施例的半导体器件包括为存储单元提供的存储单元和选择栅极晶体管。 选择栅极晶体管的栅电极具有三栅结构，其中形成在选择栅极晶体管的沟道上方的栅极绝缘膜的上表面被设定为高于栅极绝缘膜的元件隔离区的上表面的一部分 选择栅极晶体管。

公开(公告)号：US08212306B2

公开(公告)日：2012-07-03

申请号：US12721757

申请日：2010-03-11

申请人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

发明人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

摘要： A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.

摘要翻译： 半导体存储装置具有半导体基板，在半导体基板上形成有规定间隔的多个第一绝缘膜，在第一方向上形成在第一绝缘膜之间的元件隔离区域，包括第一电荷累积膜的浮栅电极 形成在所述第一绝缘膜上的第二电荷累积膜，形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜，以及形成的第三电荷累积膜 在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度，形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜， 形成在电荷累积膜上的第三绝缘膜 和沿着第二方向的元件隔离区域，以及形成在第三绝缘膜上的控制栅极电极。