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公开(公告)号：US08377754B1
公开(公告)日：2013-02-19
申请号：US13269819
申请日：2011-10-10
IPC分类号： H01L21/332
CPC分类号： H01L29/66068 , H01L29/66393 , H01L29/7436
摘要： A method of forming an IC device including a latchup silicon controlled rectifier (SCR) includes forming a mask on a top surface of a substrate, wherein the mask covers a first portion of the substrate and exposes a second portion of the substrate that is located in one of an n-well and a p-well on the substrate; etching the exposed second portion of the substrate to form an etched area; forming a stress engineered junction of the latchup SCR by selective epitaxial deposition in the etched area; and removing the mask.
摘要翻译： 一种形成包括闭锁硅可控整流器（SCR）的IC器件的方法包括在衬底的顶表面上形成掩模，其中所述掩模覆盖所述衬底的第一部分并且暴露所述衬底的位于 在衬底上的n阱和p阱中的一个; 蚀刻所述基板的暴露的第二部分以形成蚀刻区域; 通过选择性外延沉积在蚀刻区域中形成闭锁SCR的应力工程结; 并取下面罩。
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公开(公告)号：US08373267B2
公开(公告)日：2013-02-12
申请号：US13196404
申请日：2011-08-02
CPC分类号： H01L29/66386 , H01L24/06 , H01L27/0262 , H01L29/74 , H01L29/7436 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： A structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. The first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.
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53.发明授权Methods, design structures, and systems for current mode logic (CML) differential driver ESD protection circuitry 失效电流模式逻辑（CML）差分驱动器ESD保护电路的方法，设计结构和系统公开(公告)号：US07826188B2
公开(公告)日：2010-11-02
申请号：US12140485
申请日：2008-06-17
CPC分类号： H03F3/45188 , H01L27/0251 , H03F1/52 , H03F1/523 , H03F2203/45466 , H03F2203/45486 , H03F2203/45504
摘要： A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further comprises an integrated circuit having a differential driver, comprising: a first driver and a second driver forming the differential driver, the drivers are coupled in parallel between a first voltage source and a second voltage source; a first switch coupled to the first driver and configured to turn off the first driver during an ESD event such that the first driver sustains stress during the ESD event; and a second switch coupled to the second driver and configured to turn off the second driver during the ESD event such that the second driver sustains stress during the ESD event.
摘要翻译： 在机器可读数据存储介质上编码的硬件描述语言（HDL）设计结构，所述HDL设计包括在计算机辅助设计系统中处理时的元件，生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示。 HDL设计结构还包括具有差分驱动器的集成电路，包括：形成差分驱动器的第一驱动器和第二驱动器，驱动器并联耦合在第一电压源和第二电压源之间; 第一开关，其耦合到所述第一驱动器并且被配置为在ESD事件期间关闭所述第一驱动器，使得所述第一驱动器在所述ESD事件期间保持应力; 以及耦合到所述第二驱动器并被配置为在所述ESD事件期间关闭所述第二驱动器的第二开关，使得所述第二驱动器在所述ESD事件期间维持应力。
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公开(公告)号：US09219056B2
公开(公告)日：2015-12-22
申请号：US13431347
申请日：2012-03-27
IPC分类号： H01L27/06 , H01L21/20 , H01L21/33 , H01L27/02 , H01L21/8249 , H01L21/84 , H01L29/06 , H01L27/12
CPC分类号： H01L27/0262 , G06F17/5072 , H01L21/8249 , H01L21/845 , H01L27/0255 , H01L27/06 , H01L27/1211 , H01L29/06
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译： 无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 将绝缘体上半导体衬底的器件层的一部分图案化以形成器件区域。 在外延层和器件区域中形成第一导电类型的阱。 在阱中形成第二导电类型的掺杂区域并且限定与阱的一部分的结。 外延层包括与器件区域的外侧壁间隔开的外侧壁。 可以对器件层的另一部分进行构图以形成翅片型场效应晶体管的鳍片。
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公开(公告)号：US09058995B2
公开(公告)日：2015-06-16
申请号：US13440514
申请日：2012-04-05
CPC分类号： H01L27/027 , H01L29/0692 , H01L29/456 , H01L29/7436 , H01L29/7824 , H01L29/7835
摘要： Device structures, design structures, and fabrication methods for a drain-extended metal-oxide-semiconductor (DEMOS) transistor. A first well of a first conductivity type and a second well of a second conductivity type are formed in a device region. The first and second wells are juxtaposed to define a p-n junction. A first doped region of the first conductivity type and a doped region of the second conductivity type are in the first well. The first doped region of the first conductivity type is separated from the second well by a first portion of the first well. The doped region of the second conductivity type is separated from the second well by a second portion of the first well. A second doped region of the first conductivity type, which is in the second well, is separated by a portion of the second well from the first and second portions of the first well.
摘要翻译： 漏极延伸金属氧化物半导体（DEMOS）晶体管的器件结构，设计结构和制造方法。 第一导电类型的第一阱和第二导电类型的第二阱形成在器件区域中。 第一和第二井并列以定义p-n结。 第一导电类型的第一掺杂区域和第二导电类型的掺杂区域位于第一阱中。 第一导电类型的第一掺杂区域与第一阱的第一部分与第二阱分离。 第二导电类型的掺杂区域与第一阱的第二部分与第二阱分离。 在第二阱中的第一导电类型的第二掺杂区域由第一阱的第一和第二部分的第二阱的一部分分开。
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56.发明授权Device structures compatible with fin-type field-effect transistor technologies 有权器件结构与鳍式场效应晶体管技术相兼容公开(公告)号：US08759194B2
公开(公告)日：2014-06-24
申请号：US13455732
申请日：2012-04-25
IPC分类号： H01L21/76
CPC分类号： H01L27/1211 , G06F17/5068 , H01L21/3086 , H01L21/845
摘要： Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.
摘要翻译： 鳍式场效应晶体管集成电路技术的器件结构，设计结构和制造方法。 构成器件结构的电极的第一和第二鳍片均由第一半导体材料构成。 第二翅片邻近第一翅片形成以限定分隔第一和第二翅片的间隙。 位于间隙中的是由第二半导体材料构成的层。
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公开(公告)号：US08363367B2
公开(公告)日：2013-01-29
申请号：US12632015
申请日：2009-12-07
申请人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , G06F17/5045
摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.
摘要翻译： 提供了一种用于电力过应力（EOS）保护的半导体电路。 半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。 连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。 特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。 可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。
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58.发明授权Structure for a stacked power clamp having a BigFET gate pull-up circuit 有权具有BigFET栅极上拉电路的堆叠式功率钳的结构公开(公告)号：US08010927B2
公开(公告)日：2011-08-30
申请号：US12127245
申请日：2008-05-27
申请人： Robert J. Gauthier, Jr. , Junjun Li
发明人： Robert J. Gauthier, Jr. , Junjun Li
CPC分类号： G06F17/5045 , H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.
摘要翻译： 用于保护集成电路芯片免受ESD事件的静电放电（ESD）保护电路的设计结构。 ESD保护电路的设计结构包括一堆BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及用于触发BigFET栅极驱动器以响应于ESD事件来驱动BigFET栅极的触发器。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。 栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。
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59.发明授权Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits 失效绝缘体上半导体高压器件结构，制造这种器件结构的方法，以及高压电路的设计结构公开(公告)号：US07772651B2
公开(公告)日：2010-08-10
申请号：US12013101
申请日：2008-01-11
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Christopher S. Putnam , Mitra Souvick
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L21/84
摘要： High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.
摘要翻译： 高电压器件结构，使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法，以及高压电路的设计结构。 使用绝缘体上半导体（SOI）衬底形成的平面器件结构包括位于两个栅电极之间的半导体本体。 栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。 电介质层将每个栅电极与半导体本体分开。 这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，其可以与形成器件隔离区的工艺同时发生。
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60.发明授权Method for improved triggering and oscillation suppression of ESD clamping devices 失效改善ESD钳位装置触发和振荡抑制的方法公开(公告)号：US07646573B2
公开(公告)日：2010-01-12
申请号：US12133424
申请日：2008-06-05
CPC分类号： H01L27/0266
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.
摘要翻译： 用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。 功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。 第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。
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