公开(公告)号：US20070283172A1

公开(公告)日：2007-12-06

申请号：US11420820

申请日：2006-05-30

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

IPC: G06F1/00

CPC classification number: G06F1/26

Abstract: A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.

Abstract translation: 提供了一种通过基于电路中的电压感测的节流执行单元来减轻电源和配电系统噪声响应的系统。 感测单元感测电路的电压。 感测单元确定另一个执行单元的执行是否会导致电路电压降至阈值以下。 响应于确定另一执行单元的执行将导致电路电压降低到阈值水平以下，执行单元被调节。

公开(公告)号：US06885098B2

公开(公告)日：2005-04-26

申请号：US10408485

申请日：2003-04-07

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: H01L23/498 ,  H01L23/053

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  H01L2924/00

Abstract: Aspects for routing in multilayer ceramic substrates that reduces via depth and avoids via bulge are described. The aspects include providing a multilayer ceramic substrate with at least two redistribution layers. Vias for each of a plurality of signal lines are jogged on at least a second redistribution layer of the at least two redistribution layers. Further, the aspects include providing the second redistribution layer no more than seven layers deep in the multilayer ceramic substrate.

Abstract translation: 描述了减少通孔深度并避免通过凸起的多层陶瓷基板中布线的方面。 这些方面包括提供具有至少两个再分布层的多层陶瓷基板。 多个信号线中的每一个的通孔在至少两个再分配层的至少第二再分布层上被点动。 此外，这些方面包括在多层陶瓷衬底中提供不超过七层深度的第二再分配层。

公开(公告)号：US06769108B2

公开(公告)日：2004-07-27

申请号：US10099776

申请日：2002-03-14

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: G06F1750

CPC classification number: G06F17/5068 ,  G06F2217/40

Abstract: A system for minimizing the length of the longest diagonal interconnection. A multiple chip module may comprise a first chip connected to a second chip located diagonally to the first chip. The first and second chip are interconnected by one or more interconnections commonly referred to as diagonal interconnections. Since the one or more diagonal interconnections between the first chip and the second chip are interconnected between a set of pins on each chip that form a triangular pattern, the longest diagonal interconnection is substantially the same length as the length of the longest orthogonal interconnection. Furthermore, since the one or more diagonal interconnections between the first chip and the second chip are interconnected between a set of pins on each chip that form a triangular pattern, the longest diagonal interconnection is substantially the same length as the length of the second longest diagonal interconnection.

公开(公告)号：US06617243B1

公开(公告)日：2003-09-09

申请号：US09637315

申请日：2000-08-10

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: H01L2314

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  H01L2924/00

Abstract: Aspects for routing in multilayer ceramic substrates that reduces via depth and avoids via bulge are described. The aspects include providing a multilayer ceramic substrate with at least two redistribution layers. Vias for each of a plurality of signal lines are jogged on at least a second redistribution layer of the at least two redistribution layers. Further, the aspects include providing the second redistribution layer no more than seven layers deep in the multilayer ceramic substrate.

Abstract translation: 描述了减少通孔深度并避免通过凸起的多层陶瓷基板中布线的方面。 这些方面包括提供具有至少两个再分布层的多层陶瓷衬底。 多个信号线中的每一个的通孔在至少两个再分配层的至少第二再分布层上被点动。 此外，这些方面包括在多层陶瓷衬底中提供不超过七层深度的第二再分配层。

公开(公告)号：US08625300B2

公开(公告)日：2014-01-07

申请号：US13603761

申请日：2012-09-05

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H05K1/14

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有带状段互连的通孔上的参考平面空隙的制造电路允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

公开(公告)号：US08593621B2

公开(公告)日：2013-11-26

申请号：US12771245

申请日：2010-04-30

Applicant: Kevin J. Bills ,  Mahesh Bohra ,  Hong T. Dang ,  Rohan U. Mandrekar ,  Roger D. Weekly

Inventor： Kevin J. Bills ,  Mahesh Bohra ,  Hong T. Dang ,  Rohan U. Mandrekar ,  Roger D. Weekly

IPC: G01N21/00

CPC classification number: G01M11/3154

Abstract: For testing whether an optical fiber is properly connected to a device, a beam of light is output to the optical fiber. An intensity is detected of light reflected by the device back through the optical fiber in response to the beam of light. In response to the detected intensity, a determination is made of whether the optical fiber is properly connected to the device.

Abstract translation: 为了测试光纤是否正确连接到设备，光束被输出到光纤。 通过响应于光束，通过光纤反射的装置反射的光的强度被检测。 响应于检测到的强度，确定光纤是否正确连接到设备。

公开(公告)号：US08451020B2

公开(公告)日：2013-05-28

申请号：US12894325

申请日：2010-09-30

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: H03K19/00

CPC classification number: H01L27/0203 ,  B23K26/38 ,  B23K2101/38

Abstract: A function of an integrated circuit is selectively disabled by mechanical intervention at a module that contains the integrated circuit, such as drilling a hole through the module, cutting a slot in the module or burning a hole with a laser through the laser. Mechanical destruction of the module at a predetermined spot disrupts a function enable signal that is otherwise provide through wires of the module to a connection with the integrated circuit. Without the function enable signal from the module wires to the integrated circuit connector, the function associated with the function enable signal cannot run on the integrated circuit.

Abstract translation: 集成电路的功能通过在包含集成电路的模块上的机械干预来选择性地禁用，例如在模块中钻孔，切割模块中的槽或通过激光器用激光烧孔。 在预定点处的模块的机械破坏破坏了另外通过模块的导线与集成电路的连接提供的功能使能信号。 没有功能使能信号从模块导线到集成电路连接器，与功能使能信号相关的功能不能在集成电路上运行。

公开(公告)号：US20130087918A1

公开(公告)日：2013-04-11

申请号：US13687218

申请日：2012-11-28

Applicant: Roger D. Weekly ,  Yaping Zhou

Inventor： Roger D. Weekly ,  Yaping Zhou

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract translation: 一种用于分配电源和接地引脚以及用于球栅阵列半导体封装的单端或差分信号对的改进的系统和方法。 在某些实施例中，系统使用六边形图案，其中网格可以由多个嵌套的六边形图案表示。

公开(公告)号：US08399981B2

公开(公告)日：2013-03-19

申请号：US13614102

申请日：2012-09-13

Applicant: Roger D. Weekly ,  Yaping Zhou

Inventor： Roger D. Weekly ,  Yaping Zhou

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract translation: 一种用于分配电源和接地引脚以及用于球栅阵列半导体封装的单端或差分信号对的改进的系统和方法。 在某些实施例中，系统使用六边形图案，其中网格可以由多个嵌套的六边形图案表示。

公开(公告)号：US20130055192A1

公开(公告)日：2013-02-28

申请号：US13611609

申请日：2012-09-12

Applicant: John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

Inventor： John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: H05K1/144 ,  G11C5/025 ,  H05K1/113 ,  H05K1/114 ,  H05K1/141 ,  H05K3/0058 ,  H05K3/325 ,  H05K2201/044 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10719 ,  H05K2201/2009

Abstract: Mechanisms for interconnecting and distributing signals and power between PCBs are provided. A first PCB having land grid arrays (LGAs) and a first wiring layer designed for interconnect components on the first PCB, and a second wiring layer for connecting the components to a second PCB, are provided. The second PCB has opposed parallel first and second surfaces, the first surface having a LGA. A wiring layer designed to interconnect components on the second PCB, and a layer for interconnecting the components on the second PCB with the components on the first PCB, are provided. A first interposer couples to a LGA of a first surface of the first PCB and connects a component to the first PCB. A second interposer is sandwiched between and couples to a LGA of a second surface of the first PCB and to the LGA of the first surface of the second PCB.

Abstract translation: 提供了在PCB之间互连和分配信号和电源的机制。 提供了具有地面栅格阵列（LGAs）的第一PCB和为第一PCB上的互连部件设计的第一布线层以及用于将部件连接到第二PCB的第二布线层。 第二PCB具有相对的平行的第一和第二表面，第一表面具有LGA。 设置用于互连第二PCB上的组件的布线层和用于将第二PCB上的组件与第一PCB上的组件互连的层。 第一插入器耦合到第一PCB的第一表面的LGA并将部件连接到第一PCB。 第二插入件夹在第一PCB的第二表面的LGA和第二PCB的第一表面的LGA之间并耦合到第二PCB的第二表面的LGA。