公开(公告)号：US20100019221A1

公开(公告)日：2010-01-28

申请号：US12177533

申请日：2008-07-22

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： H01L45/00

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1683 ,  Y10S438/90

摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells. Each memory cell in the plurality of memory cells comprises a diode comprising doped semiconductor material and a dielectric spacer on the diode and defining an opening, the dielectric spacer having sides self-aligned with sides of the diode. Each memory cell further comprises a memory element on the dielectric spacer and including a portion within the opening contacting a top surface of the diode.

摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括多个存储器单元。 多个存储单元中的每个存储器单元包括二极管，其包括掺杂半导体材料和二极管上的电介质间隔物，并且限定开口，所述电介质间隔物具有与二极管的侧面自对准的侧面。 每个存储单元还包括介质间隔物上的存储元件，并且包括开口内接触二极管顶表面的部分。

公开(公告)号：US07642125B2

公开(公告)日：2010-01-05

申请号：US11855979

申请日：2007-09-14

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： H01L21/06

CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1683

摘要： An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.

摘要翻译： 通过在触点阵列上形成分离层，在分离层上形成隔离层并使用光刻工艺在隔离层中形成阵列的存储元件开口来制造“蘑菇”型相变存储器单元的阵列。 通过补偿由光刻工艺产生的存储元件开口的尺寸变化的过程，在存储元件开口内形成蚀刻掩模。 蚀刻掩模用于蚀刻穿过分离层以限定电极开口的阵列。 电极材料沉积在电极开口内; 并且存储元件形成在存储元件开口内。 存储元件和底部电极是自对准的。

公开(公告)号：US20090189138A1

公开(公告)日：2009-07-30

申请号：US12020717

申请日：2008-01-28

申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch ,  Chieh Fang Chen

发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch ,  Chieh Fang Chen

IPC分类号： H01L45/00 ,  H01L21/4763

CPC分类号： H01L45/04 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L21/76808 ,  H01L21/76816 ,  H01L27/222 ,  H01L27/24 ,  H01L43/08 ,  H01L45/145

摘要： A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.

摘要翻译： 存储单元包括在底部电极层上方具有第一介电层的存储单元层，在第一介电层上的第二电介质层和位于第二介电层上的顶部电极。 电介质层限定具有由第一电极层和底部电极限定的第一部分和由第二电介质层和顶部电极限定的第二部分的通孔。 存储元件位于通孔内并与顶部和底部电极电接触。 通孔的第一和第二部分可以分别包括收缩的能量集中区和扩大区。 收缩区域可以具有小于用于形成通孔的扩大区域的过程的最小特征尺寸的宽度。 还公开了一种用于制造存储单元的方法。

公开(公告)号：US20090095948A1

公开(公告)日：2009-04-16

申请号：US11871813

申请日：2007-10-12

申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch

发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch

IPC分类号： H01L47/00 ,  H01L21/00

CPC分类号： H01L45/04 ,  G11C13/0004 ,  G11C17/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1683

摘要： Programmable resistive memory cells are accessed by semiconductor diode structures. Manufacturing methods and integrated circuits for programmable resistive elements with such diode structures are also disclosed.

摘要翻译： 可编程电阻存储单元由半导体二极管结构访问。 还公开了具有这种二极管结构的可编程电阻元件的制造方法和集成电路。

公开(公告)号：US20090072215A1

公开(公告)日：2009-03-19

申请号：US11855979

申请日：2007-09-14

申请人： Hsiang Lan Lung ,  Chung Hon Lam

发明人： Hsiang Lan Lung ,  Chung Hon Lam

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1683

摘要： An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.

摘要翻译： 通过在触点阵列上形成分离层，在分离层上形成隔离层并使用光刻工艺在隔离层中形成阵列的存储元件开口来制造“蘑菇”型相变存储器单元的阵列。 通过补偿由光刻工艺产生的存储元件开口的尺寸变化的过程，在存储元件开口内形成蚀刻掩模。 蚀刻掩模用于蚀刻穿过分离层以限定电极开口的阵列。 电极材料沉积在电极开口内; 并且存储元件形成在存储元件开口内。 存储元件和底部电极是自对准的。

公开(公告)号：US20090027950A1

公开(公告)日：2009-01-29

申请号：US11828717

申请日：2007-07-26

申请人： Chung Hon Lam ,  Hsiang-Lan Lung

发明人： Chung Hon Lam ,  Hsiang-Lan Lung

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/74

摘要： An embodiment of our invention includes a method of programming at least one phase change memory block, the at least one block comprising at least one phase change memory cell, the at least one cell comprising at least one phase change material. The method includes the steps of transitioning all cells within the at least one block to a first state and, after all cells within the at least one block have been transitioned to the first state, transitioning at least one cell within the at least one block to at least a second state. Transitioning a cell to the at least second state is faster than transitioning a cell to the first state. At least the step of transitioning all cells within the at least one block to a first state may include transitioning all cells within the at least one block in a substantially simultaneous manner.

摘要翻译： 本发明的实施例包括编程至少一个相变存储器块的方法，所述至少一个块包括至少一个相变存储器单元，所述至少一个单元包括至少一个相变材料。 该方法包括以下步骤：将至少一个块内的所有小区转换到第一状态，并且在至少一个块内的所有小区已经转变到第一状态之后，将至少一个块内的至少一个小区转换为 至少第二状态。 将单元转换到至少第二状态比将单元转换到第一状态更快。 至少将至少一个块内的所有小区转换到第一状态的步骤可以包括以基本上同时的方式转换至少一个块内的所有小区。

公开(公告)号：US20090001336A1

公开(公告)日：2009-01-01

申请号：US11771033

申请日：2007-06-29

申请人： Nazmul Habib ,  Chung Hon Lam ,  Robert McMahon

发明人： Nazmul Habib ,  Chung Hon Lam ,  Robert McMahon

IPC分类号： H01L45/00

CPC分类号： G01K11/06 ,  G01K7/16 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

摘要： A block of phase change material located in a semiconductor chip is reset to an amorphous state. The block of phase change material may be connected to an internal resistance measurement circuit that can transmit the measured resistance data to input/output pads either in an analog output format or in a digital output format. Depending on the ambient temperature, the resistance of the block of phase change material changes. By measuring a fractional resistance change compared to the resistance of the phase change material at a calibration temperature, the temperature of the region around the phase change material can be accurately measured. A logic decoder and an input/output circuit may be employed between the internal resistance measurement circuit and the input/output pads. A plurality of temperature sensing circuits containing phase change material blocks may be employed in the semiconductor chip to enable an accurate temperature profiling during chip operation.

摘要翻译： 位于半导体芯片中的相变材料块被重置为非晶态。 相变材料块可以连接到可以以模拟输出格式或数字输出格式将测量的电阻数据传输到输入/输出焊盘的内部电阻测量电路。 根据环境温度，相变材料块的电阻变化。 通过测量与校准温度下的相变材料的电阻相比的分数电阻变化，可以精确地测量相变材料周围的区域的温度。 可以在内部电阻测量电路和输入/输出焊盘之间采用逻辑解码器和输入/输出电路。 可以在半导体芯片中采用包含相变材料块的多个温度检测电路，以便在芯片操作期间能够进行精确的温度分布。

公开(公告)号：US07351666B2

公开(公告)日：2008-04-01

申请号：US11378492

申请日：2006-03-17

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/528 ,  H01L2224/06 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.

摘要翻译： 一种用于制造的集成电路和方法，包括第一和第二结构，每个结构包括一组子光刻线，以及在端部处连接到至少一个子光刻线的接触着陆段。 第一和第二结构被嵌套，使得亚光刻线以平行方式设置在宽度内，并且第一结构的接触着陆段被设置在相对于子平版印刷线的相对侧的相对侧 第二结构的接触着陆段。 用于第一和第二结构的接触着陆段包括在宽度尺寸内，其中宽度包括通过光刻实现的最小特征尺寸的四倍的尺寸。

公开(公告)号：US06420777B2

公开(公告)日：2002-07-16

申请号：US09031251

申请日：1998-02-26

申请人： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

发明人： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

IPC分类号： H01L2358

CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3185 ,  Y10S438/97

摘要： A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.

摘要翻译： 提供了用于SiO 2的反应离子蚀刻的方法和用于这种蚀刻中的蚀刻阻挡层。 具有小于约0.8且优选化学计量量为0.75的六至奈比（x：y）的氮化硅（SixNy）阻挡层对正移动离子污染提供优异的回弹性，但蚀刻选择性差。 然而，六至氮（x：y）的比例为1.0或更大的氮化硅阻挡层相对于SiO 2具有优异的蚀刻选择性，但对于移动离子污染的正面阻挡性差。 在掺杂硅衬底上形成氮化硅屏障，该阻挡层具有两个部分。 一个部分相对于二氧化硅具有比第二部分更大的蚀刻选择性，并且第二部分比第一部分具有更大的对正性可移动离子透射的抵抗力。 与硅衬底相邻的一个部分的硅氮比小于约0.8。 在第一部分顶部形成的第二部分形成硅与氮的比大于约0.8。 优选地，两个部分一起为约50至约100纳米厚。

公开(公告)号：US06403482B1

公开(公告)日：2002-06-11

申请号：US09605726

申请日：2000-06-28

申请人： Nivo Rovedo ,  Chung Hon Lam

发明人： Nivo Rovedo ,  Chung Hon Lam

IPC分类号： H01L21302

CPC分类号： H01L29/66636 ,  H01L29/0653 ,  H01L29/41766

摘要： Transistors having self-aligned dielectric layers under the source/drain contacts are formed by constructing transistors up to the LDD implant; etching STI oxide selective to Si and nitride to form a self-aligned contact recess; depositing an insulating layer in the bottom of the contact recess; recessing the insulating layer to leave room for a conductive contact layer; depositing the contact layer to make contact on a vertical surface to the Si underneath the gate sidewalls; recessing the contact layer; forming interlayer dielectric and interconnect to complete the circuit.

摘要翻译： 在源极/漏极触点下方具有自对准电介质层的晶体管通过构造直到LDD注入的晶体管来形成; 蚀刻对Si和氮化物有选择性的STI氧化物以形成自对准的接触凹部; 在接触凹部的底部沉积绝缘层; 使绝缘层凹陷以留下导电接触层的空间; 沉积接触层以在与栅极侧壁下方的Si的垂直表面上接触; 使接触层凹陷; 形成层间电介质和互连以完成电路。