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183 条记录 (耗时 0.038 秒)

    Data storage medium and apparatus and method for reproducing the data from the same
    51.
    发明授权
    Data storage medium and apparatus and method for reproducing the data from the same 有权
    数据存储介质以及从其再现数据的装置和方法

    公开(公告)号：US07162147B2

    公开(公告)日：2007-01-09

    申请号：US11428468

    申请日：2006-07-03

    申请人： Yoshihiro Mori ,  Masayuki Kozuka

    发明人： Yoshihiro Mori ,  Masayuki Kozuka

    IPC分类号： H04N5/91 ,  H04N5/781

    CPC分类号： G11B27/105 ,  G11B27/3027 ,  G11B27/329 ,  G11B27/34 ,  G11B2220/2562 ,  H04N5/775 ,  H04N9/8042 ,  H04N9/8063 ,  H04N9/8227

    摘要： A data storage medium having stored thereon includes an audio sequence including at least one audio stream; at least one video stream; and reproduction control information for controlling reproduction of the at least one audio stream and the at least one video stream. The reproduction control information includes reproduction order information defining the order of at least one video stream, among the at least one video stream stored on the data storage medium, which is to be reproduced in synchronization with the audio sequence.

    摘要翻译： 其上存储的数据存储介质包括包括至少一个音频流的音频序列; 至少一个视频流; 以及用于控制至少一个音频流和至少一个视频流的再现的再现控制信息。 再现控制信息包括定义要与音频序列同步地再现的在数据存储介质上存储的至少一个视频流中的至少一个视频流的顺序的再现顺序信息。

    HEMODIALYSIS APPARATUS AND METHOD FOR HEMODIALYSIS
    52.
    发明申请
    HEMODIALYSIS APPARATUS AND METHOD FOR HEMODIALYSIS 审中-公开
    HEMODIALYSIS设备和HEMODIALYSIS方法

    公开(公告)号：US20060226079A1

    公开(公告)日：2006-10-12

    申请号：US11278745

    申请日：2006-04-05

    申请人： Yoshihiro Mori ,  Masahiro Toyoda

    发明人： Yoshihiro Mori ,  Masahiro Toyoda

    IPC分类号： B01D65/00

    CPC分类号： A61M1/16 ,  A61M1/1611 ,  A61M1/1613 ,  A61M1/341 ,  A61M2205/52 ,  A61M2230/207

    摘要： A hemodialysis apparatus includes a dialyzing device, a measuring device and a calculation device. The dialyzing device dialyzes and ultrafiltrates blood of a patient circulating extracorporeally to perform hemodialysis treatment. The measuring device measures a variation rate of a body weight of the patient and a variation rate of a predetermined blood benchmark during the hemodialysis treatment using the dialyzing device. The calculation device calculates, during the hemodialysis treatment, a parameter relating the variation rate of the body weight and the variation rate of the predetermined blood benchmark to each other, and correlating to a dry weight of the patient.

    摘要翻译： 血液透析装置包括透析装置，测量装置和计算装置。 透析装置透析和超滤体外循环的患者的血液进行血液透析治疗。 测量装置测量使用透析装置的血液透析治疗期间患者体重的变化率和预定血液基准的变化率。 计算装置在血液透析治疗期间，计算将体重的变化率与预定血液基准的变化率相关联的参数，并与患者的干重相关联。

    Semiconductor device
    55.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06974987B2

    公开(公告)日：2005-12-13

    申请号：US10477924

    申请日：2003-02-14

    申请人： Hisashi Ogawa ,  Isao Miyanaga ,  Koji Eriguchi ,  Takayuki Yamada ,  Kazuichiro Itonaga ,  Yoshihiro Mori

    发明人： Hisashi Ogawa ,  Isao Miyanaga ,  Koji Eriguchi ,  Takayuki Yamada ,  Kazuichiro Itonaga ,  Yoshihiro Mori

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10882 ,  H01L27/10829 ,  H01L27/10894 ,  Y10S257/905 ,  Y10S257/908

    摘要： A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 30. In a memory cell transistor, a source diffusion layer 18 is covered with two dielectric sidewalls 25a and 25b in the memory cell transistor so that no silicide layer is formed on the source diffusion layer 18. A plate contact 31 is provided to pass through the inter-level dielectric 30 and connect a shield line 33 to a plate electrode 16b. The shield line 33 is arranged in the same interconnect layer as the bit line 32.

    摘要翻译： 存储单元晶体管和沟槽电容器设置在存储区域中，CMOS的两个晶体管都设置在逻辑电路区域中。 提供了位线接触件31和在层间电介质30上延伸的位线32。 在存储单元晶体管中，源极扩散层18被存储单元晶体管中的两个电介质侧壁25a和25b覆盖，使得在源极扩散层18上不形成硅化物层。 提供板触点31以通过层间电介质30并将屏蔽线33连接到平板电极16b。 屏蔽线33布置在与位线32相同的互连层中。

    Semiconductor memory and method for fabricating the same
    56.
    发明授权
    Semiconductor memory and method for fabricating the same 失效
    半导体存储器及其制造方法

    公开(公告)号：US06916705B2

    公开(公告)日：2005-07-12

    申请号：US10656153

    申请日：2003-09-08

    申请人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

    发明人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242

    CPC分类号： H01L27/10852 ,  H01L27/10894 ,  H01L28/55 ,  Y10S438/926

    摘要： In a memory cell of a DRAM, that is, a semiconductor memory, a bit line connected to a bit line plug and a local interconnect are provided on a first interlayer insulating film. A connection conductor film of TiAlN is provided on the top and side faces of an upper barrier metal and side faces of a Pt film and a BST film. No contact is formed above the Pt film used for forming an upper electrode, and the upper electrode is connected to an upper interconnect (namely, a Cu interconnect) through the connection conductor film, a dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, the characteristic degradation of a capacitor insulating film can be prevented.

    摘要翻译： 在第一层间绝缘膜上设置DRAM的存储单元，即半导体存储器，连接到位线插头和局部互连的位线。 TiAlN的连接导体膜设置在上阻挡金属的顶面和侧面以及Pt膜和BST膜的侧面上。 在用于形成上电极的Pt膜上方没有形成接触，并且上电极通过连接导体膜，虚拟下电极，虚拟电池插头和本地连接到上互连（即Cu互连） 互连。 由于Pt膜没有暴露于还原气氛中，所以可以防止电容器绝缘膜的特性劣化。

    Switching power supply apparatus with blanking pulse generator
    57.
    发明授权
    Switching power supply apparatus with blanking pulse generator 失效
    具有消隐脉冲发生器的开关电源设备

    公开(公告)号：US06914789B2

    公开(公告)日：2005-07-05

    申请号：US10742392

    申请日：2003-12-22

    申请人： Tomoko Kinoshita ,  Yoshihiro Mori

    发明人： Tomoko Kinoshita ,  Yoshihiro Mori

    IPC分类号： H02M3/28 ,  H02M3/335

    CPC分类号： H02M3/33507 ,  H02M2001/0032 ,  Y02B70/16

    摘要： A switching power supply apparatus is provided, wherein an optimal blanking interval can be obtained for an entire load range. The switching power supply apparatus is configured such that an on-blanking pulse signal generating circuit 31 generates a blanking pulse signal based on an error voltage signal VEAO, and sets a blanking interval that corresponds to the load condition. For example, the reference voltage and the voltage value of the error voltage signal VEAO are compared and the blanking pulse signal that shortens the blanking interval is generated during a light load, that is, when the voltage value of the error voltage signal VEAO is less than or equal to the reference voltage.

    摘要翻译： 提供了一种开关电源装置，其中可以在整个负载范围内获得最佳消隐间隔。 开关电源装置被配置为使得消隐脉冲信号发生电路31基于误差电压信号VEAO产生消隐脉冲信号，并设置与负载条件相对应的消隐间隔。 例如，比较误差电压信号VEAO的参考电压和电压值，并且在轻负载期间产生缩短消隐间隔的消隐脉冲信号，即，当误差电压信号VEAO的电压值较小时 大于或等于参考电压。

    Switching power supply
    58.
    发明授权
    Switching power supply 失效
    开关电源

    公开(公告)号：US06879501B2

    公开(公告)日：2005-04-12

    申请号：US10754604

    申请日：2004-01-12

    申请人： Yoshihiro Mori

    发明人： Yoshihiro Mori

    IPC分类号： H02M3/28 ,  H02J1/02 ,  H02M3/335 ,  H02M7/122

    CPC分类号： H02M3/33523 ,  H02M1/32 ,  H02M2001/009

    摘要： The present invention provides a switching power supply which has an overcurrent protection characteristic with a small number of components. The switching power supply includes a regulator from a drain and an auxiliary winding VCC, a drain current detection circuit for detecting a current applied to a switching element, an oscillation circuit for outputting a clock signal of a constant frequency, a feedback signal control circuit for detecting a control signal from the secondary side and controlling current applied to the switching element, a clamping circuit for controlling the maximum value of current applied to the switching element, and a clamp voltage variable circuit for changing a clamp voltage of the clamping circuit and an oscillation frequency of the oscillation circuit according to a voltage of VCC.

    摘要翻译： 本发明提供一种具有少数部件的过电流保护特性的开关电源。 开关电源包括来自漏极和辅助绕组VCC的调节器，用于检测施加到开关元件的电流的漏极电流检测电路，用于输出恒定频率的时钟信号的振荡电路，反馈信号控制电路 检测来自次级侧的控制信号并控制施加到开关元件的电流，用于控制施加到开关元件的电流的最大值的钳位电路和用于改变钳位电路的钳位电压的钳位电压可变电路和 振荡电路的振荡频率根据VCC的电压。

    Semiconductor memory and method for fabricating the same
    59.
    发明授权
    Semiconductor memory and method for fabricating the same 失效
    半导体存储器及其制造方法

    公开(公告)号：US06642564B2

    公开(公告)日：2003-11-04

    申请号：US10196229

    申请日：2002-07-17

    申请人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

    发明人： Hisashi Ogawa ,  Yoshihiro Mori ,  Akihiko Tsuzumitani

    IPC分类号： H01L27108

    CPC分类号： H01L27/10852 ,  H01L27/10894 ,  H01L28/55 ,  Y10S438/926

    摘要： In a memory cell of a DRAM, that is, a semiconductor memory, a bit line connected to a bit line plug and a local interconnect are provided on a first interlayer insulating film. A connection conductor film of TiAlN is provided on the top and side faces of an upper barrier metal and side faces of a Pt film and a BST film. No contact is formed above the Pt film used for forming an upper electrode, and the upper electrode is connected to an upper interconnect (namely, a Cu interconnect) through the connection conductor film, a dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, the characteristic degradation of a capacitor insulating film can be prevented.

    摘要翻译： 在第一层间绝缘膜上设置DRAM的存储单元，即半导体存储器，连接到位线插头和局部互连的位线。 TiAlN的连接导体膜设置在上阻挡金属的顶面和侧面以及Pt膜和BST膜的侧面上。 在用于形成上电极的Pt膜上方没有形成接触，并且上电极通过连接导体膜，虚拟下电极，虚拟电池插头和本地连接到上互连（即Cu互连） 互连。 由于Pt膜没有暴露于还原气氛中，所以可以防止电容器绝缘膜的特性劣化。