公开(公告)号：US20200013434A1

公开(公告)日：2020-01-09

申请号：US16168168

申请日：2018-10-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: G11C5/06 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  G11C5/10 ,  G11C16/28 ,  G11C16/24 ,  G11C16/08

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the I/O pads.

公开(公告)号：US09929174B1

公开(公告)日：2018-03-27

申请号：US15337235

申请日：2016-10-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki Mizutani ,  Hiroyuki Ogawa ,  Fumiaki Toyama ,  Masaaki Higashitani ,  Fumitaka Amano ,  Kota Funayama ,  Akihiro Ueda

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/786 ,  H01L29/792 ,  H01L27/11568 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/0692 ,  H01L29/78642 ,  H01L29/7926

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures including a memory film and a vertical semiconductor channel are formed through the alternating stack in an array configuration. Backside trenches extending along a lengthwise direction are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers. Filling of the backside recesses with electrically conductive layers can be performed without voids or with minimal voids by arranging the memory stack structures with a non-uniform pitch. The non-uniform pitch may be along the direction perpendicular to the lengthwise direction such that the nearest neighbor distance among the memory stack structures is at a minimum between the backside trenches. Alternatively or additionally, the pitch may be modulated along the lengthwise direction to provide wider spacing regions that extend perpendicular to the lengthwise direction.

公开(公告)号：US12125814B2

公开(公告)日：2024-10-22

申请号：US17667238

申请日：2022-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05007 ,  H01L2224/05073 ,  H01L2224/05565 ,  H01L2224/05573 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2224/0801 ,  H01L2224/08147 ,  H01L2224/0903 ,  H01L2224/0913 ,  H01L2224/29187 ,  H01L2224/29188 ,  H01L2224/29575 ,  H01L2224/29687 ,  H01L2224/32145 ,  H01L2224/80895 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.

公开(公告)号：US11646283B2

公开(公告)日：2023-05-09

申请号：US17357120

申请日：2021-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Masaaki Higashitani ,  Ramy Nashed Bassely Said

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/036 ,  H01L2224/05073 ,  H01L2224/05561 ,  H01L2224/08145 ,  H01L2224/80895

Abstract: A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a bonded assembly.

公开(公告)号：US20230081623A1

公开(公告)日：2023-03-16

申请号：US17666657

申请日：2022-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hua-Ling Cynthia Hsu ,  Masaaki Higashitani ,  YenLung Li ,  Chen Chen

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  H03M13/11 ,  H03M13/00

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

公开(公告)号：US11562975B2

公开(公告)日：2023-01-24

申请号：US17244387

申请日：2021-04-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: A bonded assembly of a first semiconductor die and a second semiconductor die includes first and second semiconductor dies. The first semiconductor die includes first semiconductor devices, first metal interconnect structures embedded in first dielectric material layers, and first metal bonding pads laterally surrounded by a semiconductor material layer. The second semiconductor die includes second semiconductor devices, second metal interconnect structures embedded in second dielectric material layers, and second metal bonding pads that include primary metal bonding pads and auxiliary metal bonding pads. The auxiliary metal bonding pads are bonded to the semiconductor material layer through metal-semiconductor compound portions formed by reaction of surface portions of the semiconductor material layer and an auxiliary metal bonding pad. The primary metal bonding pads are bonded to the first metal bonding pads by metal-to-metal bonding.

公开(公告)号：US11552094B2

公开(公告)日：2023-01-10

申请号：US17031080

申请日：2020-09-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Murshed Chowdhury ,  Masaaki Higashitani ,  Johann Alsmeier

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and an array of memory opening fill structures extending through the alternating stack, an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies, and a drain-select-level isolation strip including an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion.

公开(公告)号：US11538708B2

公开(公告)日：2022-12-27

申请号：US16867818

申请日：2020-05-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shoichi Murakami ,  Shigeru Nakatsuka ,  Syo Fukata ,  Yusuke Osawa ,  Shigehiro Fujino ,  Masaaki Higashitani

IPC: H01L21/683 ,  H01L21/67 ,  H01J37/32 ,  H01L21/687

Abstract: An apparatus includes an electrostatic chuck and located within a vacuum enclosure. A plurality of conductive plates can be embedded in the electrostatic chuck, and a plurality of plate bias circuits can be configured to independently electrically bias a respective one of the plurality of conductive plates. Alternatively or additionally, a plurality of spot lamp zones including a respective set of spot lamps can be provided between a bottom portion of the vacuum enclosure and a backside surface of the electrostatic chuck. The plurality of conductive plates and/or the plurality of spot lamp zones can be employed to locally modify chucking force and to provide local temperature control.

公开(公告)号：US11424215B2

公开(公告)日：2022-08-23

申请号：US17094543

申请日：2020-11-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L23/00 ,  H01L25/00 ,  H01L27/11582 ,  H01L21/50 ,  H01L23/532 ,  H01L27/11556 ,  H01L21/60

Abstract: A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.

公开(公告)号：US11348901B1

公开(公告)日：2022-05-31

申请号：US17106884

申请日：2020-11-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: A first bonding unit is provided, which includes a first substrate, a first passivation dielectric layer, and first bonding pads. A second bonding unit is provided, which includes a second substrate, a second passivation dielectric layer, and second bonding pads including bonding pillar structures. Solder material portions are formed on physically exposed surfaces of the first bonding pads. The second bonding unit is attached to the first bonding unit by bonding the at least one of the bonding pillar structures to a respective solder material portion.