公开(公告)号：US10978490B2

公开(公告)日：2021-04-13

申请号：US16535698

申请日：2019-08-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunichi Ito ,  Toshinari Sasaki ,  Miyuki Hosoba ,  Junichiro Sakata

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/45 ,  G09G3/20 ,  H01L29/66

Abstract: An object is to control composition and a defect of an oxide semiconductor, another object is to increase a field effect mobility of a thin film transistor and to obtain a sufficient on-off ratio with a reduced off current. A solution is to employ an oxide semiconductor whose composition is represented by InMO3(ZnO)m, where M is one or a plurality of elements selected from Ga, Fe, Ni, Mn, Co, and Al, and m is preferably a non-integer number of greater than 0 and less than 1. The concentration of Zn is lower than the concentrations of In and M. The oxide semiconductor has an amorphous structure. Oxide and nitride layers can be provided to prevent pollution and degradation of the oxide semiconductor.

公开(公告)号：US10396236B2

公开(公告)日：2019-08-27

申请号：US15685005

申请日：2017-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Miyuki Hosoba ,  Suzunosuke Hiraishi

IPC: H01L33/00 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/32

Abstract: Disclosed is a semiconductor device comprising a thin film transistor and wirings connected to the thin film transistor, in which the thin film transistor has a channel formation region in an oxide semiconductor layer, and a copper metal is used for at least one of a gate electrode, a source electrode, a drain electrode, a gate wiring, a source wiring, and a drain wiring. The extremely low off current of the transistor with the oxide semiconductor layer contributes to reduction in power consumption of the semiconductor device. Additionally, the use of the copper metal allows the combination of the semiconductor device with a display element to provide a display device with high display quality and negligible defects, which results from the low electrical resistance of the wirings and electrodes formed with the copper metal.

公开(公告)号：US10079306B2

公开(公告)日：2018-09-18

申请号：US15368984

申请日：2016-12-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Miyuki Hosoba ,  Junichiro Sakata ,  Hideaki Kuwabara

IPC: H01L29/00 ,  H01L27/00 ,  H01L29/786 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/66 ,  H01L29/45 ,  H01L29/51 ,  G02F1/167 ,  G02F1/136 ,  H01L27/32 ,  G02F1/1339 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1368 ,  G09G3/34 ,  G09G3/36

CPC classification number: H01L29/78606 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F1/167 ,  G02F2001/13606 ,  G02F2201/123 ,  G09G3/344 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3262 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

公开(公告)号：US09812465B2

公开(公告)日：2017-11-07

申请号：US14804508

申请日：2015-07-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichiro Sakata ,  Toshinari Sasaki ,  Miyuki Hosoba

IPC: H01L29/10 ,  H01L29/12 ,  H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/127 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

公开(公告)号：US09379141B2

公开(公告)日：2016-06-28

申请号：US14692077

申请日：2015-04-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiroki Ohara ,  Junichiro Sakata ,  Toshinari Sasaki ,  Miyuki Hosoba

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L27/127 ,  H01L21/477 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1274 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78693

Abstract: An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.

公开(公告)号：US09130046B2

公开(公告)日：2015-09-08

申请号：US14228663

申请日：2014-03-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichiro Sakata ,  Toshinari Sasaki ,  Miyuki Hosoba

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/127 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Abstract translation: 目的在于提供一种利用具有稳定电特性的晶体管稳定工作的显示装置。 在使用其中使用氧化物半导体层作为沟道形成区域的晶体管的显示装置的制造中，栅电极进一步设置在至少施加到驱动电路的晶体管上。 在将氧化物半导体层用于沟道形成区域的晶体管的制造中，对氧化物半导体层进行热处理以脱水或脱氢; 因此，存在于氧化物半导体层和栅极绝缘层之间的界面处的杂质，其存在于氧化物半导体层下方并与氧化物半导体层接触，以及氧化物半导体层与设置在该氧化物半导体层上的与保护绝缘层接触的界面 可以减少氧化物半导体层。

公开(公告)号：US09024314B2

公开(公告)日：2015-05-05

申请号：US13969808

申请日：2013-08-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiroki Ohara ,  Junichiro Sakata ,  Toshinari Sasaki ,  Miyuki Hosoba

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

Abstract: An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.

公开(公告)号：US08809856B2

公开(公告)日：2014-08-19

申请号：US13784908

申请日：2013-03-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Miyuki Hosoba ,  Junichiro Sakata ,  Hideaki Kuwabara

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78606 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F1/167 ,  G02F2001/13606 ,  G02F2201/123 ,  G09G3/344 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3262 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Abstract translation: 目的在于提供一种半导体器件，其具有可以有效地减少布线之间的寄生电容的结构。 在使用氧化物半导体层的底栅薄膜晶体管中，用作沟道保护层的氧化物绝缘层形成在与栅电极层重叠的氧化物半导体层的一部分上方并与其形成接触，同时氧化物 形成覆盖层叠氧化物半导体层的周边部（包括侧面）的绝缘层。 此外，以与沟道保护层不重叠的方式形成源极电极层和漏极电极层。 因此，提供了源极电极层和漏电极层上的绝缘层与氧化物半导体层接触的结构。

公开(公告)号：US08772093B2

公开(公告)日：2014-07-08

申请号：US13717806

申请日：2012-12-18

Applicant: Semiconductor Energy Laboratory Co. Ltd.

Inventor： Shunpei Yamazaki ,  Miyuki Hosoba ,  Junichiro Sakata ,  Hideaki Kuwabara

IPC: H01L21/84 ,  H01L21/00

CPC classification number: H01L29/78606 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F1/167 ,  G02F2001/13606 ,  G02F2201/123 ,  G09G3/344 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3262 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Abstract translation: 目的在于提供一种半导体器件，其具有可以有效地减少布线之间的寄生电容的结构。 在使用氧化物半导体层的底栅薄膜晶体管中，用作沟道保护层的氧化物绝缘层形成在与栅电极层重叠的氧化物半导体层的一部分上方并与其形成接触，同时氧化物 形成覆盖层叠氧化物半导体层的周边部（包括侧面）的绝缘层。 此外，以与沟道保护层不重叠的方式形成源极电极层和漏极电极层。 因此，提供了源极电极层和漏电极层上的绝缘层与氧化物半导体层接触的结构。

公开(公告)号：US08698970B2

公开(公告)日：2014-04-15

申请号：US13939468

申请日：2013-07-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Junichiro Sakata ,  Masashi Tsubuku ,  Kengo Akimoto ,  Miyuki Hosoba ,  Masayuki Sakakura ,  Yoshiaki Oikawa

IPC: G02F1/136

CPC classification number: H01L21/477 ,  G02F1/133345 ,  G02F1/1368 ,  H01L21/02565 ,  H01L21/02664 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1251 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.