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    METHOD FOR CONTROLLING HEIGHT OF A FIN STRUCTURE
    51.
    发明申请
    METHOD FOR CONTROLLING HEIGHT OF A FIN STRUCTURE 审中-公开
    控制精细结构高度的方法

    公开(公告)号：US20150380258A1

    公开(公告)日：2015-12-31

    申请号：US14314384

    申请日：2014-06-25

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh ,  Kejia Wang

    IPC: H01L21/308 ,  H01L29/205 ,  H01L29/78

    CPC classification number: H01L29/205 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

    Abstract: Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights.

    Abstract translation: 描述了形成翅片结构的方法和结构，同时在大面积上以高均匀性控制翅片结构的高度。 根据一些方面，在衬底上形成包括由衬底分离并通过间隔层彼此分离的第一蚀刻停止层和第二蚀刻停止层的多层结构。 沟槽可以通过第一和第二蚀刻停止层形成。 可以在沟槽中形成缓冲层，将沟槽填充到大致在第一蚀刻停止层的位置处的水平。 半导体层可以形成在缓冲层的上方并被回蚀刻到第二蚀刻停止层以形成高均匀高度的半导体鳍片。

    Methods for forming vertical and sharp junctions in finFET structures
    53.
    发明授权
    Methods for forming vertical and sharp junctions in finFET structures 有权
    在finFET结构中形成垂直和尖锐结的方法

    公开(公告)号：US09202920B1

    公开(公告)日：2015-12-01

    申请号：US14447727

    申请日：2014-07-31

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Qing Liu ,  Chun-chen Yeh ,  Ruilong Xie ,  Xiuyu Cai

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

    Abstract: Methods and structures for forming short-channel finFETs with vertical and abrupt source and drain junctions are described. During fabrication, source and drain regions of the finFET may be recessed vertically and laterally under gate spacers. A buffer having a high dopant density may be formed on vertical sidewalls of the channel region after recessing the fin. Raised source and drain structures may be formed at the recessed source and drain regions. The raised source and drain structures may impart strain to the channel region.

    Abstract translation: 描述了用于形成具有垂直和突然的源极和漏极结的短沟道finFET的方法和结构。 在制造期间，finFET的源极和漏极区域可以在栅极间隔物下方垂直和横向地凹陷。 具有高掺杂浓度的缓冲器可以在凹陷鳍片之后形成在沟道区域的垂直侧壁上。 可以在凹陷的源极和漏极区域形成升高的源极和漏极结构。 升高的源极和漏极结构可能对沟道区域施加应变。

    SEMICONDUCTOR DEVICE INCLUDING VERTICALLY SPACED SEMICONDUCTOR CHANNEL STRUCTURES AND RELATED METHODS
    54.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING VERTICALLY SPACED SEMICONDUCTOR CHANNEL STRUCTURES AND RELATED METHODS 有权
    包括垂直间隔半导体通道结构和相关方法的半导体器件

    公开(公告)号：US20150108573A1

    公开(公告)日：2015-04-23

    申请号：US14060874

    申请日：2013-10-23

    Applicant: GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

    Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0886

    Abstract: A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.

    Abstract translation: 制造半导体器件的方法可以包括在衬底上形成交替的第一和第二半导体层的至少一个叠层。 第一半导体层可以包括第一半导体材料，第二半导体层可以包括第二半导体材料。 第一半导体材料可以相对于第二半导体材料可选择性地蚀刻。 该方法还可以包括去除至少一个堆叠和衬底的部分以限定其暴露的侧壁，在暴露的侧壁上形成相应的间隔物，蚀刻通过至少一个堆叠和衬底的凹槽以限定多个间隔开的柱，选择性蚀刻 来自多个柱的第一半导体材料离开第二半导体材料结构，在相对端通过相应的间隔件支撑，并且形成与第二半导体材料结构相邻的至少一个栅极。

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