公开(公告)号：US09437504B2

公开(公告)日：2016-09-06

申请号：US14802407

申请日：2015-07-17

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu ,  Balasubramanian Pranatharthiharan ,  Shom Ponoth

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/6653 ,  H01L29/6656

Abstract: On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.

Abstract translation: 在第一半导体材料基板上沉积由第二半导体材料形成的上覆牺牲层。 在第一区域中，在牺牲层上形成第一半导体材料区域。 在第二区域中，在牺牲层上形成第二半导体材料区域。 图案化第一半导体材料区域以限定第一FinFET鳍片。 图案化第二半导体材料区域以限定第二FinFET鳍片。 翅片各自被盖和侧壁间隔物覆盖。 然后选择性地去除由第二半导体材料形成的牺牲层，以在第一和第二FinFET鳍片下面形成开口（这些鳍片由侧壁间隔件支撑）。 然后每个翅片下面的开口填充有用于将鳍片的半导体材料与衬底隔离的介电材料。

公开(公告)号：US20160149038A1

公开(公告)日：2016-05-26

申请号：US14983070

申请日：2015-12-29

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/06 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

Abstract translation: 在外延生长的晶体中存在小面或空隙，表明晶体生长已被缺陷或某些材料边界中断。 在形成应变硅晶体管的源极和漏极区域的硅化合物的外延生长期间，可以抑制刻面。 已经观察到，当某些硅化合物的外延层相邻于氧化物边界生长时，可以发生刻面，但是当外延层生长在邻近硅边界或与氮化物边界相邻时，不会发生刻面。 因为硅化合物的外延生长通常在填充有氧化物的隔离沟槽附近是必要的，所以在这些区域中抑制刻面的技术是特别有意义的。 本文提出的一种这样的技术是使隔离沟槽与SiN对准，以在氧化物和预期外延生长的区域之间提供阻挡层。

公开(公告)号：US09252052B2

公开(公告)日：2016-02-02

申请号：US14096563

申请日：2013-12-04

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L29/00 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

公开(公告)号：US09000491B2

公开(公告)日：2015-04-07

申请号：US14309409

申请日：2014-06-19

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

IPC: H01L29/745 ,  H01L27/148 ,  H01L21/311 ,  H01L29/10 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L29/04 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78

Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

Abstract translation: 可以在半导体器件区域上形成绝缘层，并以基本上减少或防止下面的沟道区域的蚀刻量的方式进行蚀刻。 可以在栅极区域和半导体器件区域上形成第一绝缘层。 可以在第一绝缘层上形成第二绝缘层。 可以在第二绝缘层上形成第三绝缘层。 可以使用第一蚀刻工艺蚀刻第三绝缘层的一部分。 可以使用与第一蚀刻工艺不同的至少第二蚀刻工艺来蚀刻第三绝缘层的蚀刻部分下方的第一绝缘层和第二绝缘层的一部分。

公开(公告)号：US08987082B2

公开(公告)日：2015-03-24

申请号：US13906758

申请日：2013-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878

Abstract: A method of making a semiconductor device includes forming a sacrificial layer above a semiconductor layer. Portions of the sacrificial layer are selectively removed to define a first set of spaced apart sacrificial fins over a first region of the semiconductor layer, and a second set of spaced apart sacrificial fins over a second region of the semiconductor layer. An isolation trench is formed in the semiconductor layer between the first and second regions. The isolation trench and spaces are filled with a dielectric material. The first and second sets of sacrificial fins are removed to define respective first and second sets of fin openings. The first set of fin openings is filled to define a first set of semiconductor fins for a first conductivity-type transistor, and the second set of fin openings is filled to define a second set of semiconductor fins for a second conductivity-type transistor.

Abstract translation: 制造半导体器件的方法包括在半导体层上形成牺牲层。 牺牲层的一部分被选择性地去除以在半导体层的第一区域上限定出第一组隔开的牺牲散热片，以及在半导体层的第二区域上的第二组隔开的牺牲散热片。 在第一和第二区域之间的半导体层中形成隔离沟槽。 绝缘沟槽和空间填充有电介质材料。 去除第一组和第二组牺牲翅片以限定相应的第一组和第二组翅片开口。 填充第一组翅片开口以限定用于第一导电型晶体管的第一组半导体鳍片，并且填充第二组翅片开口以限定用于第二导电型晶体管的第二组半导体鳍片。

公开(公告)号：US20150008521A1

公开(公告)日：2015-01-08

申请号：US14494979

申请日：2014-09-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/78 ,  H01L21/266 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/7849

Abstract: A transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

Abstract translation: 晶体管包括主体和构造成对身体的一部分施加应力的半导体区域。 例如，施加晶体管的沟道可以增加沟道中载流子的迁移率，从而可以降低晶体管的“导通”电阻。 例如，可以掺杂PFET的衬底，源极/漏极区域或者衬底和源/漏极区域，以对沟道进行压缩应力，从而增加沟道中空穴的迁移率。 或者，可以掺杂NFET的衬底，源极/漏极区域或衬底和源极/漏极区域两者以使通道拉伸应力，以增加沟道中电子的迁移率。

公开(公告)号：US20140357029A1

公开(公告)日：2014-12-04

申请号：US13906758

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC.

Inventor： NICOLAS LOUBET ,  Prasanna Khare

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878

Abstract: A method of making a semiconductor device includes forming a sacrificial layer above a semiconductor layer. Portions of the sacrificial layer are selectively removed to define a first set of spaced apart sacrificial fins over a first region of the semiconductor layer, and a second set of spaced apart sacrificial fins over a second region of the semiconductor layer. An isolation trench is formed in the semiconductor layer between the first and second regions. The isolation trench and spaces are filled with a dielectric material. The first and second sets of sacrificial fins are removed to define respective first and second sets of fin openings. The first set of fin openings is filled to define a first set of semiconductor fins for a first conductivity-type transistor, and the second set of fin openings is filled to define a second set of semiconductor fins for a second conductivity-type transistor.

Abstract translation: 制造半导体器件的方法包括在半导体层上形成牺牲层。 牺牲层的一部分被选择性地去除以在半导体层的第一区域上限定出第一组隔开的牺牲散热片，以及在半导体层的第二区域上的第二组隔开的牺牲散热片。 在第一和第二区域之间的半导体层中形成隔离沟槽。 绝缘沟槽和空间填充有电介质材料。 去除第一组和第二组牺牲翅片以限定相应的第一组和第二组翅片开口。 填充第一组翅片开口以限定用于第一导电型晶体管的第一组半导体鳍片，并且填充第二组翅片开口以限定用于第二导电型晶体管的第二组半导体鳍片。

公开(公告)号：US20140353753A1

公开(公告)日：2014-12-04

申请号：US13906677

申请日：2013-05-31

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/7848 ,  H01L29/785

Abstract: Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET.

Abstract translation: 改进的鳍状场效应晶体管（FinFET）器件及其制造方法。 一方面，一种用于制造FinFET器件的方法包括：提供生长有硅外延层的硅衬底。 衬底上的牺牲结构由外延层形成。 在牺牲结构和暴露的衬底部分之上形成覆盖硅层，所述覆盖硅层具有均匀厚度的上部和下部，并且中间部分插入在不均匀厚度的上部和下部之间并且具有形成角度。 半导体散热片阵列由覆盖硅层和覆盖层上形成的非共形层形成。 去除牺牲结构，并且在通道区域下填充隔离结构的所得空隙。 在FinFET的鳍合并期间，在源极/漏极区域中形成源极和漏极。

公开(公告)号：US20140099773A1

公开(公告)日：2014-04-10

申请号：US14096515

申请日：2013-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS, INC.

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/768 ,  H01L21/762

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.