公开(公告)号：US09570513B2

公开(公告)日：2017-02-14

申请号：US14150596

申请日：2014-01-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/108 ,  H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L29/08

CPC classification number: H01L27/2445 ,  H01L27/226 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732 ,  H01L45/04 ,  H01L45/06 ,  H01L45/16

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

Abstract translation: 本公开涉及包括晶体管的集成电路，该晶体管包括第一和第二导电端子以及控制端子。 集成电路还包括第一介电层，导电层和第二介电层的堆叠，第一导电端子包括形成在第一介电层中的第一半导体区域，该控制端子包括形成在第一介电层中的第二半导体区域 导电层，第二导电端子包括形成在第二介电层中的第三半导体区域。

公开(公告)号：US09425239B2

公开(公告)日：2016-08-23

申请号：US14737372

申请日：2015-06-11

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Julien Delalleau

IPC: H01L27/24 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L23/528 ,  H01L29/423 ,  H01L21/265 ,  H01L21/762 ,  H01L27/115 ,  H01L29/78

CPC classification number: H01L43/12 ,  H01L21/26513 ,  H01L21/76224 ,  H01L23/528 ,  H01L27/11507 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L29/42356 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.

Abstract translation: 本公开涉及一种半导体衬底上的存储器，包括：至少一条数据线，至少一条选择线，至少一条参考线，至少一个存储单元，包括选择晶体管，该选择晶体管具有连接到选择线的控制栅极， 连接到可变阻抗元件的第一导电端子，所述选择晶体管和所述参考线耦合到所述数据线的所述可变阻抗元件，所述选择晶体管包括在形成于所述衬底中的沟槽中产生的嵌入垂直栅极和与所述衬底相对的沟道区域 沟槽的第一面，位于耦合到可变阻抗元件的衬底的表面上的第一深掺杂区域和第二掺杂区域之间。

公开(公告)号：US08999796B2

公开(公告)日：2015-04-07

申请号：US14074059

申请日：2013-11-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/112 ,  H01L27/105 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/283 ,  H01L21/768

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/768 ,  H01L27/1052 ,  H01L27/11206 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating at least one cell of a semiconducting component includes positioning a first conducting polysilicon-type layer on a substrate, above an insulating oxide-type layer. The production of at least one trench within the first conducting layer is included to form two electrically unlinked distinct conducting parts intended to form two transistor gates of respectively two distinct twin cells.

Abstract translation: 一种用于制造半导体元件的至少一个元件的方法包括将第一导电多晶硅型层定位在绝缘氧化物层上方的衬底上。 包括在第一导电层内产生至少一个沟槽以形成两个电气不连接的不同的导电部件，用于形成分别为两个不同的双电池的两个晶体管栅极。

公开(公告)号：US08921219B2

公开(公告)日：2014-12-30

申请号：US14173249

申请日：2014-02-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin

IPC: H01L21/3205 ,  H01L29/788 ,  H01L29/66 ,  B82Y10/00 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/66825 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/7885

Abstract: A process for fabricating a transistor may include forming source and drain regions in a substrate, and forming a floating gate having electrically conductive nanoparticles able to accumulate electrical charge. The process may include deoxidizing part of the floating gate located on the source side, and oxidizing the space resulting from the prior deoxidation so as to form an insulating layer on the source side.

Abstract translation: 制造晶体管的工艺可以包括在衬底中形成源区和漏区，以及形成具有能够积累电荷的导电纳米颗粒的浮栅。 该方法可以包括使位于源侧的浮动栅极的一部分脱氧，并且氧化由先前脱氧产生的空间，从而在源极侧上形成绝缘层。

公开(公告)号：US20140191179A1

公开(公告)日：2014-07-10

申请号：US14150596

申请日：2014-01-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2445 ,  H01L27/226 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732 ,  H01L45/04 ,  H01L45/06 ,  H01L45/16

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

Abstract translation: 本公开涉及包括晶体管的集成电路，该晶体管包括第一和第二导电端子以及控制端子。 集成电路还包括第一介电层，导电层和第二介电层的堆叠，第一导电端子包括形成在第一介电层中的第一半导体区域，该控制端子包括形成在第一介电层中的第二半导体区域 导电层，第二导电端子包括形成在第二介电层中的第三半导体区域。