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    Semiconductor memory devices
    51.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11887648B2

    公开(公告)日：2024-01-30

    申请号：US17362138

    申请日：2021-06-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeho Hong ,  Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

    IPC: H01L29/66 ,  G11C11/39 ,  G11C11/402 ,  H01L29/749 ,  H01L27/102

    CPC classification number: G11C11/4023 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/66363 ,  H01L29/749

    Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

    SEMICONDUCTOR DEVICES INCLUDING SEMICONDUCTOR PATTERN
    52.
    发明公开
    SEMICONDUCTOR DEVICES INCLUDING SEMICONDUCTOR PATTERN 审中-公开

    公开(公告)号：US20230163132A1

    公开(公告)日：2023-05-25

    申请号：US18098174

    申请日：2023-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Huijung Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

    IPC: H01L27/102 ,  H01L29/74

    CPC classification number: H01L27/1027 ,  H01L29/742

    Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

    SEMICONDUCTOR DEVICE
    53.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230075559A1

    公开(公告)日：2023-03-09

    申请号：US17741219

    申请日：2022-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Dongsoo Woo ,  Kyunghwan Lee

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/10

    Abstract: A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.

    Three-dimensional semiconductor memory devices with increased integration
    55.
    发明授权
    Three-dimensional semiconductor memory devices with increased integration 有权

    公开(公告)号：US11456313B2

    公开(公告)日：2022-09-27

    申请号：US16710198

    申请日：2019-12-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Kohji Kanamori ,  Minhan Shin

    IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/1157

    Abstract: Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a stack structure that includes gate electrodes on a substrate. The three-dimensional semiconductor memory device includes a first vertical structure, a second vertical structure, a third vertical structure, and a fourth vertical structure that penetrate the stack structure and are sequentially arranged in a zigzag shape along a first direction. Moreover, the three-dimensional semiconductor memory device includes a first bit line that extends in the first direction. The first bit line vertically overlaps the second vertical structure and the fourth vertical structure. Centers of the second and fourth vertical structures are spaced apart at the same distance from the first bit line. The first vertical structure is spaced apart at a first distance from the first bit line. The third vertical structure is spaced apart at a second distance from the first bit line.

    SEMICONDUCTOR DEVICES
    58.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220028975A1

    公开(公告)日：2022-01-27

    申请号：US17225716

    申请日：2021-04-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Sungwon Yoo ,  Jaeho Hong

    IPC: H01L29/10 ,  H01L29/06 ,  H01L29/786

    Abstract: A semiconductor device includes a gate electrode on a substrate, a channel surrounding sidewalls of the gate electrode on the substrate, and source/drain electrodes on the substrate at opposite sides of the gate electrode in a first direction parallel to an upper surface of the substrate. A thickness of the channel from the gate electrode to the source/drain electrodes in a horizontal direction parallel to the upper surface of the substrate is not constant but varies in a vertical direction perpendicular to the upper surface of the substrate.

    SEMICONDUCTOR MEMORY DEVICE INCLUDING VARIABLE RESISTANCE LAYER
    59.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING VARIABLE RESISTANCE LAYER 审中-公开

    公开(公告)号：US20200343307A1

    公开(公告)日：2020-10-29

    申请号：US16657453

    申请日：2019-10-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Kohji Kanamori

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor memory device includes a stack structure comprising a plurality of insulating layers and a plurality of interconnection layers that are alternately and repeatedly stacked. A pillar structure is disposed on a side surface of the stack structure. The pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and positioned between insulating pillar and the stack structure. A channel layer is disposed on the variable resistance layer and is positioned between the variable resistance layer and the stack structure. A gate dielectric layer is disposed on the channel layer and is positioned between the plurality of interconnection layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.

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