公开(公告)号：US11004985B2

公开(公告)日：2021-05-11

申请号：US16793162

申请日：2020-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hun Lee ,  Dong Woo Kim ,  Dong Chan Suh ,  Sun Jung Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/092

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US10930668B2

公开(公告)日：2021-02-23

申请号：US16272265

申请日：2019-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu Edward Cho ,  Seok Hoon Kim ,  Myung Ii Kang ,  Geo Myung Shin ,  Seung Hun Lee ,  Jeong Yun Lee ,  Min Hee Choi ,  Jeong Min Choi

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

公开(公告)号：US10896957B2

公开(公告)日：2021-01-19

申请号：US15992401

申请日：2018-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namkyu Edward Cho ,  Seung Soo Hong ,  Geum Jung Seong ,  Seung Hun Lee ,  Jeong Yun Lee

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/306 ,  H01L27/11 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

公开(公告)号：US10693017B2

公开(公告)日：2020-06-23

申请号：US16435263

申请日：2019-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hun Lee ,  Dong Woo Kim ,  Dong Chan Suh ,  Sun Jung Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L27/092 ,  B82Y10/00 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US10669664B2

公开(公告)日：2020-06-02

申请号：US15172084

申请日：2016-06-02

Applicant: Samsung Electronics Co., Ltd

Inventor： Tae-Kil Kim ,  Young Jin Um ,  Kyu Nam Lee ,  Sung Mo Lee ,  Seung Hun Lee

IPC: D06F37/40 ,  D06F35/00 ,  D06F37/30 ,  D06F23/04 ,  D06F37/38 ,  D06F33/02

Abstract: In accordance with an aspect of the present disclosure, a washing apparatus including a main motor configured to generate a rotational force and provide the rotational force to a washing shaft; a coupling disposed above the main motor and selectively transmitting the rotational force of the main motor to a spin-drying shaft by vertically moving; a clutch motor configured to generate a tensile force in a radial direction of the coupling; a clutch lever configured to decouple the main motor from the coupling by moving the coupling upward using the tensile force of the clutch motor; and a controller configured to rotate the main motor in a mode switching section from a spin-drying mode, in which the coupling is coupled to the main motor, to a washing mode, in which the coupling is decoupled from the main motor, or from the washing mode to the spin-drying mode.

公开(公告)号：US20190258538A1

公开(公告)日：2019-08-22

申请号：US16122146

申请日：2018-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui Chung BYUN ,  Yoen Hwa Lee ,  Seung Hun Lee

IPC: G06F11/10 ,  G11C29/00 ,  G11C7/10 ,  G11C29/44

Abstract: A memory device includes a plurality of memory chips storing and outputting data in response to a control command and an address command, at least one ECC memory chip providing an error check and correction (ECC) function on the data stored and output by the plurality of the memory chips, and a controller, marking a memory chip in which a defective memory cell is detected among the plurality of memory chips, as a defective memory chip, storing data of the defective memory chip in the ECC memory chip, and controlling the defective memory chip to execute a post package repair (PPR).

公开(公告)号：US10312152B2

公开(公告)日：2019-06-04

申请号：US15818657

申请日：2017-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong ,  Seung Hun Lee ,  Pan Kwi Park ,  Seung Ryul Lee

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66 ,  H01L27/04

Abstract: A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.

公开(公告)号：US10008575B2

公开(公告)日：2018-06-26

申请号：US15298746

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Chan Suh ,  Yong Suk Tak ,  Gi Gwan Park ,  Mi Seon Park ,  Moon Seung Yang ,  Seung Hun Lee ,  Poren Tang

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L29/42376 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/7831 ,  H01L29/78696

Abstract: A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern.

公开(公告)号：US20170327990A1

公开(公告)日：2017-11-16

申请号：US15594492

申请日：2017-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hun Lee ,  Jun Hyun Park

IPC: D06F37/40 ,  D06F23/04 ,  D06F37/24 ,  D06F39/08 ,  D06F17/08 ,  D06F37/30 ,  D06F37/42

CPC classification number: D06F37/40 ,  D06F17/08 ,  D06F23/04 ,  D06F33/02 ,  D06F37/24 ,  D06F37/304 ,  D06F37/42 ,  D06F39/083 ,  D06F39/088 ,  D06F2202/12 ,  D06F2204/065 ,  D06F2204/10 ,  D06F2210/00

Abstract: Disclosed herein are a washing machine and a method of controlling the same. The washing machine includes a motor configured to generate a rotational force, an inverter module with a plurality of switching circuits installed therein and configured to adjust a driving current supplied to the motor, and a controller configured to detect whether a fault signal is generated by an overcurrent in the inverter module and to control opening and closing of at least one of the plurality of switching circuits based on a detection result of the occurrence of fault signal when controlling the driving of the motor.

公开(公告)号：US09406777B2

公开(公告)日：2016-08-02

申请号：US14667376

申请日：2015-03-24

Applicant: IMEC VZW ,  Samsung Electronics Co. Ltd.

Inventor： Seung Hun Lee ,  Geert Eneman

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L29/66545 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for manufacturing a transistor device comprising a channel layer is disclosed. In one example, the method includes providing a substrate, epitaxially growing a strained layer on the substrate (defect free), epitaxially growing the channel layer on the epitaxially grown strained layer, and providing a gate structure on the channel layer. In this example, the method also includes selectively etching into the channel layer and at least partially in the epitaxially grown strained layer, thereby using the gate structure as a mask, and thereby creating a protrusion extending from the substrate. The protrusion may comprise a portion of the channel layer and at least an upper portion of the epitaxially grown strained layer, and may allow for elastic relaxation in the portions.

Abstract translation: 公开了一种制造包括沟道层的晶体管器件的方法。 在一个实例中，该方法包括提供衬底，在衬底上外延生长应变层（无缺陷），外延生长外延生长的应变层上的沟道层，并在沟道层上提供栅极结构。 在该示例中，该方法还包括选择性地蚀刻到沟道层中并且至少部分地在外延生长的应变层中蚀刻，从而使用栅极结构作为掩模，从而产生从衬底延伸的突起。 突起可以包括沟道层的一部分和外延生长的应变层的至少上部，并且可以允许部分中的弹性松弛。