公开(公告)号：US07816724B2

公开(公告)日：2010-10-19

申请号：US11997464

申请日：2006-07-21

Applicant: Youseok Suh ,  Satoshi Torii ,  Lei Xue

Inventor： Youseok Suh ,  Satoshi Torii ,  Lei Xue

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/792

Abstract: A memory device (100) may include a substrate (110), a dielectric layer (210) formed on the substrate (110) and a charge storage element (220) formed on the dielectric layer (210). The memory device (100) may also include an inter-gate dielectric (230) formed on the charge storage element (220), a barrier layer (240) formed on the inter-gate dielectric (230) and a control gate (250) formed on the barrier layer (240). The barrier layer (240) prevents reaction between the control gate (250) and the inter-gate dielectric (230).

Abstract translation: 存储器件（100）可以包括衬底（110），形成在衬底（110）上的电介质层（210）和形成在电介质层（210）上的电荷存储元件（220）。 存储器件（100）还可以包括形成在电荷存储元件（220）上的栅极间电介质（230），形成在栅极间电介质（230）上的阻挡层（240）和控制栅极（250） 形成在阻挡层（240）上。 阻挡层（240）防止控制栅极（250）和栅极间电介质（230）之间的反应。

公开(公告)号：US07671403B2

公开(公告)日：2010-03-02

申请号：US11567257

申请日：2006-12-06

Applicant: Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

Inventor： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

IPC: H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

Abstract translation: 一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。 该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。 器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质 。 所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第 基质。

公开(公告)号：US20090180320A1

公开(公告)日：2009-07-16

申请号：US12411938

申请日：2009-03-26

Applicant: Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

Inventor： Satoshi Torii ,  Kazuhiro Mizutani ,  Toshio Nomura ,  Masayoshi Asano ,  Ikuto Fukuoka ,  Hiroshi Mawatari ,  Motoi Takahashi

IPC: G11C16/04 ,  H01L29/792 ,  G11C16/06

CPC classification number: G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Abstract translation: 一种非易失性半导体存储器件，包括以矩阵形式布置的存储单元阵列，每个存储单元阵列包括选择晶体管和存储单元晶体管; 控制位线电位的列解码器; 电压施加电路，控制第一字线的电位; 控制第二字线的电位的第一行解码器; 以及控制源极线的电位的第二行解码器。 列解码器由耐压低于电压施加电路和第二行解码器的电路形成。

公开(公告)号：US07501677B2

公开(公告)日：2009-03-10

申请号：US11595639

申请日：2006-11-10

Applicant: Hidehiko Shiraiwa ,  Jaeyong Park ,  Satoshi Torii ,  Hideki Arakawa ,  Masaru Yano

Inventor： Hidehiko Shiraiwa ,  Jaeyong Park ,  Satoshi Torii ,  Hideki Arakawa ,  Masaru Yano

IPC: H01L29/72

CPC classification number: H01L29/792 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

Abstract: A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.

Abstract translation: 形成在半导体衬底内的SONOS存储单元包括设置在半导体衬底上的底部电介质，设置在底部电介质上的电荷捕获材料和设置在电荷俘获材料上的顶部电介质。 此外，SONOS存储单元包括设置在顶部电介质上的字线栅极结构和用于在半导体衬底内引入至少一个反转位线的至少一个位线栅极。

公开(公告)号：US07394125B1

公开(公告)日：2008-07-01

申请号：US11361277

申请日：2006-02-24

Applicant: Jaeyong Park ,  Hidehiko Shiraiwa ,  Satoshi Torii ,  Mark T. Ramsbey

Inventor： Jaeyong Park ,  Hidehiko Shiraiwa ,  Satoshi Torii ,  Mark T. Ramsbey

IPC: H01L23/62 ,  H01L21/336

CPC classification number: H01L29/42352 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: Systems and methods of fabricating a U-shaped memory device with a recessed channel and a segmented/separated ONO layer are provided. Multibit operation is facilitated by a separated ONO layer, which includes a charge trapping region on sidewalls of polysilicon gate structures adjacent to source/drain regions. Programming and erasing of the memory cells is facilitated by the relatively short distance between acting source regions and the gate. Additionally, short channel effects are mitigated by a relatively long U-shaped channel region that travels around the recessed polysilicon gate thereby adding a depth dimension to the channel length.

Abstract translation: 提供了制造具有凹陷通道和分段/分离的ONO层的U形存储器件的系统和方法。 通过分离的ONO层促进多位操作，该ONO层包括邻近源极/漏极区的多晶硅栅极结构的侧壁上的电荷俘获区域。 存储器单元的编程和擦除由于作用源极区域和栅极之间的距离相对较短而便于实现。 此外，通过在凹陷多晶硅栅极周围移动的相对较长的U形沟道区域减轻了短沟道效应，从而增加了沟道长度的深度尺寸。

公开(公告)号：US20080135918A1

公开(公告)日：2008-06-12

申请号：US11567257

申请日：2006-12-06

Applicant: Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

Inventor： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

Abstract translation: 一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。 该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。 器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质 。 所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第 基质。

公开(公告)号：US20080079061A1

公开(公告)日：2008-04-03

申请号：US11529166

申请日：2006-09-28

Applicant: Meng Ding ,  Amol Joshi ,  Takashi Orimoto ,  Jayendra Bhakta ,  Lei Xue ,  Satoshi Torii ,  Robert Bertram Ogle

Inventor： Meng Ding ,  Amol Joshi ,  Takashi Orimoto ,  Jayendra Bhakta ,  Lei Xue ,  Satoshi Torii ,  Robert Bertram Ogle

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L29/40117 ,  H01L29/4234

Abstract: According to one exemplary embodiment, a structure, for example a flash memory cell, comprises a transistor gate dielectric stack situated on a semiconductor substrate. The transistor gate dielectric stack includes a bottom oxide layer, a silicon-rich nitride layer situated on the bottom oxide layer, a low silicon-rich nitride layer situated on the silicon-rich nitride layer, and a top oxide layer situated on the low silicon-rich nitride layer. This embodiment results in a nitride based flash memory cell having improved program speed and retention while maintaining a high erase speed. In another embodiment, a flash memory cell may further comprise a high-K dielectric layer situated on the transistor gate dielectric stack.

Abstract translation: 根据一个示例性实施例，诸如闪存单元的结构包括位于半导体衬底上的晶体管栅极电介质堆叠。 晶体管栅极电介质堆叠包括底部氧化物层，位于底部氧化物层上的富含硅的氮化物层，位于富硅氮化物层上的低富硅氮化物层和位于低硅上的顶部氧化物层 富含氮化物层。 该实施例导致基于氮化物的闪存单元具有改善的编程速度和保持，同时保持高的擦除速度。 在另一个实施例中，快闪存储器单元还可以包括位于晶体管栅极电介质叠层上的高K电介质层。

公开(公告)号：US20080023751A1

公开(公告)日：2008-01-31

申请号：US11461131

申请日：2006-07-31

Applicant: Amol Ramesh Joshi ,  Harpreet Sachar ,  YouSeok Suh ,  Shenqing Fang ,  Chih-Yuh Yang ,  Lovejeet Singh ,  David H. Matsumoto ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Scott A. Bell ,  Allison Holbrook ,  Satoshi Torii

Inventor： Amol Ramesh Joshi ,  Harpreet Sachar ,  YouSeok Suh ,  Shenqing Fang ,  Chih-Yuh Yang ,  Lovejeet Singh ,  David H. Matsumoto ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Scott A. Bell ,  Allison Holbrook ,  Satoshi Torii

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/3081 ,  H01L21/76224 ,  H01L27/115 ,  H01L29/66833

Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Abstract translation: 一种集成电路存储器系统，包括：提供衬底; 在所述衬底上形成富硅电荷存储层; 通过富硅电荷存储层沿第一方向形成第一隔离沟槽; 以及在第二方向上通过富硅电荷存储层形成第二隔离沟槽。

公开(公告)号：US20050270878A1

公开(公告)日：2005-12-08

申请号：US11199263

申请日：2005-08-09

Applicant: Satoshi Torii

Inventor： Satoshi Torii

IPC: G11C16/02 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34 ,  G11C29/56 ,  G11C29/00

CPC classification number: G11C16/3445 ,  G11C16/3436 ,  G11C16/3459

Abstract: A first decision process, which reads data from a memory cell under a first deciding condition to decide pass/fail and applies a signal to the memory cell to change an amount of charge stored in the memory cell if the data is decided as fail, and a second decision process, which reads the data from the memory cell under a second deciding condition that is relaxed rather than the first deciding condition to decide the pass/fail, are executed, and then the processes are repeated from the first decision process when the data is decided as fail in the second decision process.

Abstract translation: 第一判定处理，其在第一判定条件下从存储器单元读取数据以决定通过/失败，并且如果数据被确定为失败则将信号施加到存储器单元以改变存储在存储单元中的电荷量;以及 执行在松弛而不是决定通过/否的第一判定条件的第二判定条件下从存储器单元读取数据的第二判定处理，然后从第一判定处理重复进行处理，当第 在第二决策过程中数据被确定为失败。

公开(公告)号：US06567312B1

公开(公告)日：2003-05-20

申请号：US09689714

申请日：2000-10-13

Applicant: Satoshi Torii ,  Hideyuki Kojima ,  Hiroshi Mawatari

Inventor： Satoshi Torii ,  Hideyuki Kojima ,  Hiroshi Mawatari

IPC: G11C1604

CPC classification number: G11C16/0491 ,  G11C16/3454

Abstract: In a flash memory having, for example, a single-gate type memory cell consisting of the gate electrode provided via a thin charge trap layer on a semiconductor substrate, there is provided a non-volatile semiconductor memory that is characterized in applying a short pulse to the memory cell to partly remove the electrons from the charge trap layer after writing the data to the memory cell. This ensures the write operation reliability of non-volatile semiconductor memory such as single-gate type flash memory or the like without changing the basic structure of the memory cell array.

Abstract translation: 在具有例如由通过半导体衬底上的薄电荷陷阱层提供的栅极组成的单栅极型存储单元的闪存中，提供了一种非易失性半导体存储器，其特征在于施加短脉冲 在将数据写入到存储单元之后，将其从电荷陷阱层部分去除。 这确保了不改变存储单元阵列的基本结构的非易失性半导体存储器诸如单栅极型闪存等的写操作可靠性。