公开(公告)号：US20070035336A1

公开(公告)日：2007-02-15

申请号：US11542918

申请日：2006-10-03

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03L7/06 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C7/1072 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/095 ,  H03L7/0995

Abstract: A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding o the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by inverting a signal applied to its input and delaying the signal by a delay that is determined by a delay control signal. A selection circuit couples either the reference clock signal or the delayed clock signal to the input of the voltage controlled delay circuit. When the reference clock signal is coupled to the input of the voltage controlled delay circuit, the clock generating circuit functions as a delay-lock loop. When the delayed clock signal is coupled to the input of the voltage controlled delay circuit, the voltage controlled delay circuit operates as a ring oscillator so that the clock generating circuit functions as a phase-lock loop.

Abstract translation: 时钟发生电路包括相位比较电路，该相位比较电路产生对应于输出时钟信号和参考时钟信号的相对相位的延迟控制信号。 电压控制延迟电路通过反相施加到其输入的信号并延迟由延迟控制信号确定的延迟来产生延迟的时钟信号。 选择电路将参考时钟信号或延迟时钟信号耦合到电压控制延迟电路的输入端。 当参考时钟信号耦合到电压控制延迟电路的输入时，时钟发生电路用作延迟锁定环路。 当延迟时钟信号耦合到电压控制延迟电路的输入端时，电压控制延迟电路作为环形振荡器工作，使得时钟发生电路用作锁相环。

公开(公告)号：US20060250171A1

公开(公告)日：2006-11-09

申请号：US11124743

申请日：2005-05-09

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/10

Abstract: A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows maximum tracking bandwidth, regardless of process, voltage, or temperature variations. Central to the technique is to effectively operate the loop at a lower frequency close to its own intrinsic bandwidth (1/tLoop) instead of at the higher frequency of the clock signal (1/tCK). To do so, in one embodiment, the loop delay, tLoop, is measured or estimated prior to operation of the loop. The phase detector is then enabled to operate close to the loop frequency, 1/tLoop. In short, the phase detector is made not to see activity during useless delay times, which prevents the loop from overreacting and becoming unstable.

公开(公告)号：US06919745B2

公开(公告)日：2005-07-19

申请号：US10635913

申请日：2003-08-07

Applicant: Seong-Hoon Lee ,  Jun-Hong Ahn ,  Joo-Sun Choi

Inventor： Seong-Hoon Lee ,  Jun-Hong Ahn ,  Joo-Sun Choi

IPC: G11C11/407 ,  G06F1/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076 ,  H03K5/131 ,  H03K5/135 ,  H03L7/081 ,  H03L7/089 ,  H03L7/06

CPC classification number: G11C7/222 ,  G11C7/22 ,  G11C11/4076 ,  H03K5/133 ,  H03K5/135 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/089

Abstract: The present invention related to a ring-resister controlled DLL with fine delay line and a direct skew sensing detector, which is applicable to circuitry for compensating skew between external and internal clocks. The ring-register controlled delay locked loop according to the present invention comprises: a first delay group including a plurality of unit delay elements which are lineally coupled to each other for delaying an input clock signal; a second delay group including a plurality of unit delay elements which are circularly coupled to each other for delaying an output signal from the first delay group; a first control means for determining an amount of lineal delay in the first delay group; and a second control means for determining an amount of circular delay in the first delay group.

Abstract translation: 本发明涉及具有精细延迟线的环形阻抗控制DLL和直接偏斜感测检测器，其可应用于补偿外部和内部时钟之间的偏斜的电路。 根据本发明的环形寄存器控制的延迟锁定环包括：包括多个单元延迟元件的第一延迟组，它们彼此线性耦合以延迟输入时钟信号; 第二延迟组，包括相互循环耦合的多个单位延迟元件，用于延迟来自第一延迟组的输出信号; 第一控制装置，用于确定第一延迟组中的线路延迟量; 以及第二控制装置，用于确定第一延迟组中的循环延迟量。

公开(公告)号：US20050110554A1

公开(公告)日：2005-05-26

申请号：US10719348

申请日：2003-11-21

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: G06F7/44 ,  G06G7/12 ,  H03K5/00 ,  H03K5/13 ,  H03K5/153

CPC classification number: H03K5/13 ,  H03K5/153 ,  H03K2005/00065

Abstract: Digital phase mixers with enhanced speed are provided. A phase mixer generates a signal having a phase between the phases of two input signals based on select signals. The propagation delay of the output signal is reduced by using a first voltage source to drive the input signals and the output signal and a second voltage source, having a higher voltage than the first voltage source, to drive the select signals. The higher voltage source reduces the impedance of each transistor driven by the select signals, thus reducing the propagation delay at the output of the phase mixer. For a non-differential digital phase mixer, the propagation delay is reduced in the rising edges of the output signal. For a differential digital phase mixer, the propagation delay is reduced in the rising and falling edges of the output signal.

Abstract translation: 提供了具有增强速度的数字相位混合器。 相位混合器基于选择信号产生具有两个输入信号的相位之间的相位的信号。 通过使用第一电压源来驱动输入信号和输出信号以及具有比第一电压源更高的电压的第二电压源来驱动输出信号的传播延迟来驱动选择信号。 较高的电压源降低了由选择信号驱动的每个晶体管的阻抗，从而降低了相位混合器输出端的传播延迟。 对于非差分数字相位混频器，输出信号的上升沿传播延迟减小。 对于差分数字相位混频器，输出信号的上升沿和下降沿传播延迟减小。

公开(公告)号：US06573771B2

公开(公告)日：2003-06-03

申请号：US10136304

申请日：2002-05-02

Applicant: Seong-Hoon Lee ,  Jong Tae Kwak ,  Chang-Ki Kwon

Inventor： Seong-Hoon Lee ,  Jong Tae Kwak ,  Chang-Ki Kwon

IPC: H03L706

CPC classification number: H03L7/089 ,  H03L7/0814

Abstract: A clock synchronization circuit. The clock synchronization circuit composed of a digital DLL outputs a clock signal delayed by a variable delay line and a clock signal delayed by an additional delay cell, mixes the two clock signals, and outputs an internal clock signal having a smaller delay than a delay time of a delay cell, thereby rapidly precisely synchronizing an external clock signal and the internal clock signal. In addition, a driving unit and a control unit for adjusting a duty cycle are provided to set up a ratio of 50%, thereby improving operation performance.

Abstract translation: 时钟同步电路。 由数字DLL组成的时钟同步电路输出延迟了可变延迟线的时钟信号和延迟了附加延迟单元的时钟信号，混合两个时钟信号，并输出延迟时间比延迟时间小的内部时钟信号 延迟单元，从而快速精确地同步外部时钟信号和内部时钟信号。 此外，提供用于调整占空比的驱动单元和控制单元以设定50％的比率，从而提高操作性能。

公开(公告)号：US06476652B1

公开(公告)日：2002-11-05

申请号：US09703406

申请日：2000-10-31

Applicant: Seong-Hoon Lee ,  Jung-Il Yang

Inventor： Seong-Hoon Lee ,  Jung-Il Yang

IPC: H03L700

CPC classification number: G11C7/222 ,  G11C7/22

Abstract: A delay locked loop (DLL) is used to compensate for a skew in a synchronous dynamic random access memory. The delay locked loop includes: a delay model for delaying an external clock signal by the skew to generate a delayed clock signal; a signal generation unit, in response to the external clock signal and the delayed clock signal, for generating control signals; a first delay unit, in response to the control signals, for delaying the delayed control signal to generate a first DLL clock signal, wherein the first delay unit has a large unit delay; and a second delay unit, in response to the control signals, for delaying the first DLL clock signal to generate a second DLL clock signal, wherein the second delay means in a small unit delay.

Abstract translation: 延迟锁定环（DLL）用于补偿同步动态随机存取存储器中的偏斜。 延迟锁定环包括：用于通过偏斜延迟外部时钟信号以产生延迟的时钟信号的延迟模型; 信号生成单元，响应于所述外部时钟信号和所述延迟的时钟信号，用于产生控制信号; 第一延迟单元，响应于所述控制信号，用于延迟所述延迟的控制信号以产生第一DLL时钟信号，其中所述第一延迟单元具有大的单位延迟; 以及响应于所述控制信号的第二延迟单元，用于延迟所述第一DLL时钟信号以产生第二DLL时钟信号，其中所述第二延迟装置以小的单位延迟。

公开(公告)号：US06333896B1

公开(公告)日：2001-12-25

申请号：US09703405

申请日：2000-10-31

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: G11C800

CPC classification number: G11C7/222 ,  G11C7/22 ,  H03K5/135 ,  H03L7/0891 ,  H03L7/0995

Abstract: A delay locked loop (DLL) for compensating for a skew in a synchronous dynamic random access memory includes: a delay model means for delaying an external clock signal by the skew to generate a delayed clock signal; a control unit, in response to the external clock signal and the delayed clock signal, for generating control signals, wherein the control signal includes a control clock signal, a delayed control signal, a replication signal and a replication enable signal; a first voltage control oscillator, in response to the control clock signal and the delayed control signal, for generating a measurement oscillating signal; a second voltage controlled oscillator, in response to the replication signal and the replication enable signal, for generating a replication oscillating signal; a first unit, in response to the measurement oscillating signal and the replication oscillating signal, for generating a DLL clock signal; and a second unit for comparing a phase difference between the DLL clock signal and the external clock signal to generate a voltage control signal, wherein time periods of the measurement oscillating signal and the replication oscillating signal are changed by the voltage control signal.

Abstract translation: 用于补偿同步动态随机存取存储器中的偏斜的延迟锁定环路（DLL）包括：延迟模型装置，用于通过偏斜延迟外部时钟信号以产生延迟的时钟信号; 控制单元，响应于所述外部时钟信号和延迟的时钟信号，用于产生控制信号，其中所述控制信号包括控制时钟信号，延迟的控制信号，复制信号和复制使能信号; 第一压控振荡器，响应于所述控制时钟信号和延迟的控制信号，用于产生测量振荡信号; 第二压控振荡器，响应于所述复制信号和复制使能信号，用于产生复制振荡信号; 第一单元，响应于测量振荡信号和复制振荡信号，用于产生DLL时钟信号; 以及第二单元，用于比较DLL时钟信号和外部时钟信号之间的相位差，以产生电压控制信号，其中测量振荡信号和复制振荡信号的时间段由电压控制信号改变。

公开(公告)号：US09184711B2

公开(公告)日：2015-11-10

申请号：US13612482

申请日：2012-09-12

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03K19/0175 ,  H03F3/24 ,  H03K19/003 ,  H04L25/02

CPC classification number: H03F3/245 ,  H03K19/00315 ,  H04L25/0272

Abstract: Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit.

Abstract translation: 公开了信号系统，前置放大器，存储器件和方法，例如包括被配置为接收第一数字信号的发射器的信令系统。 发射机将对应于数字信号的发射信号提供给信号路径。 耦合到信号线的接收机系统包括前置放大器，其被耦合以从信号路径接收发送的信号。 前置放大器包括配置成提供放大信号的共栅放大晶体管。 接收机系统还包括接收器，用于从前置放大器接收放大的信号。 接收器被配置为提供对应于由接收器接收的放大信号的第二数字信号。 这样的信令系统可以用在存储器装置或任何其它电子电路中。

公开(公告)号：US20130027133A1

公开(公告)日：2013-01-31

申请号：US13191263

申请日：2011-07-26

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03F3/45

CPC classification number: H03F3/45071 ,  G11C7/062 ,  G11C7/065 ,  G11C7/12 ,  G11C2207/063 ,  H03F1/301 ,  H03F3/45179 ,  H03F2200/453 ,  H03F2200/462 ,  H03F2200/91 ,  H03F2203/45154 ,  H03F2203/45176

Abstract: Sense amplifiers including bias circuits are described. Examples include bias circuits having an adjustable width transistor. A loop gain of the bias circuit may be determined in part by the adjustable width of the transistor. Examples of sense amplifiers including amplifier stages configured to bias an input/output node to a reference voltage.

Abstract translation: 描述了包括偏置电路的感应放大器。 示例包括具有可调宽度晶体管的偏置电路。 偏置电路的环路增益可以部分地由晶体管的可调宽度确定。 读出放大器的示例包括被配置为将输入/输出节点偏置到参考电压的放大器级。

公开(公告)号：US20120243361A1

公开(公告)日：2012-09-27

申请号：US13491311

申请日：2012-06-07

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: G11C7/00 ,  H03M9/00

CPC classification number: G11C7/1051 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1072 ,  G11C11/4093 ,  G11C2207/107 ,  H03M9/00

Abstract: Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals having phases that are equally phased apart from each other. Such a data serializer may use the clock signals to generate data sample signals having a value corresponding to the value of a respective one of the parallel data digits and a timing corresponding to a respective one of the clock signals. The data sample signals may be applied to a switching circuit that includes a plurality of switches, such as respective transistors, coupled to each other in parallel between an output node and a first voltage.

Abstract translation: 提供了数据串行器，输出缓冲器，存储器件和用于串行化的方法，包括可将并行数据的数字转换为串行数据数字的对应数字流的数据串行器。 一个这样的数据串行器可以包括接收并行数据位的逻辑系统和具有彼此相位分开的相位的时钟信号。 这样的数据串行器可以使用时钟信号来产生具有对应于并行数据位中的相应一个的值的值的数据采样信号和对应于相应的一个时钟信号的定时。 数据采样信号可以被施加到包括在输出节点和第一电压之间并联耦合的多个开关（诸如相应的晶体管）的开关电路。