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公开(公告)号：US20180157366A1
公开(公告)日：2018-06-07
申请号：US14897676
申请日：2015-11-02
Inventor： Peng DU
CPC classification number: G06F3/0416 , G06F3/0412 , G06F3/044 , G06F3/047 , G06F11/00 , G09G3/006 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G2300/043
Abstract: Provided is a touch control display penal and a touch control circuit thereof. A test signal line and a touch control signal line are redesigned without any change in a conventional pixel structure, such that the touch control circuit as formed has both a test function and a touch detection function. Therefore, not only the manufacturing costs of an in-cell touch display device are effectively reduced, but the manufacturing procedure is simplified, and the yield rate of the touch display panel is improved as well.
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公开(公告)号：US20180130830A1
公开(公告)日：2018-05-10
申请号：US15863988
申请日：2018-01-08
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
IPC: H01L27/12 , H01L29/786 , H01L29/66
CPC classification number: H01L27/1288 , H01L27/124 , H01L27/1248 , H01L29/66765 , H01L29/78618 , H01L29/78678
Abstract: An LTPS array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via a contact hole. The method involves a reduced number of masks.
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公开(公告)号：US20180122840A1
公开(公告)日：2018-05-03
申请号：US15863989
申请日：2018-01-08
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
IPC: H01L27/12 , H01L29/786 , H01L29/66
CPC classification number: H01L27/1288 , H01L27/124 , H01L27/1248 , H01L29/66765 , H01L29/78618 , H01L29/78678
Abstract: An LTPS array substrate includes a substrate; a gate disposed on the substrate; a first insulating layer, a polycrystalline silicon layer, and a second insulating layer sequentially disposed on the gate; a source and a drain disposed on the second insulating layer and are electrically connected to the polycrystalline silicon layer via first contact holes formed in the second insulating layer; a passivation layer disposed on the source, the drain, and the second insulating layer and including a second contact hole formed therein to expose a surface of the drain; a third insulating layer disposed on the passivation layer in such a way that the second contact hole is exposed outside the third insulating layer; and a pixel electrode disposed on the third insulation layer and electrically connected to the drain via the second contact hole.
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公开(公告)号：US20180033385A1
公开(公告)日：2018-02-01
申请号：US14907930
申请日：2016-01-12
Inventor： Xiaoxiao WANG , Peng DU
IPC: G09G3/36 , G09G3/20 , G02F1/1345 , G02F1/13
CPC classification number: G09G3/3648 , G02F1/1303 , G02F1/13454 , G02F1/1362 , G09G3/2074 , G09G3/3677 , G09G3/3696 , G09G2230/00 , G09G2300/0408 , G09G2310/0235
Abstract: A gate driving circuit and an array substrate using the same are described. The gate driving circuit pulls up and pulls down the voltage level of the node in one display frame by a first voltage signal of a second driving module and a second voltage signal of a third driving module to control the high level and low level respectively of scan signal in the scan output terminal for sequentially writing data signal to all the first row sub-pixels, all the second row sub-pixels and all the third row sub-pixels of the one display frame in order to prevent the sub-pixels from RC delay and color deviation, thereby improving the display quality of the LCD.
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公开(公告)号：US20170357134A1
公开(公告)日：2017-12-14
申请号：US14907915
申请日：2015-12-08
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
IPC: G02F1/1362 , G02F1/1368 , G02F1/1343 , H01L27/12
CPC classification number: G02F1/136227 , G02F1/133345 , G02F1/134309 , G02F1/136209 , G02F1/1368 , G02F2001/13685 , G02F2201/121 , G02F2201/123 , G02F2202/104 , H01L27/124 , H01L27/1248
Abstract: An array substrate and a liquid crystal display device comprising the array substrate are disclosed. The array substrate comprises a pixel unit having a thin film transistor region and a through-hole region. The pixel unit comprises a glass substrate, a first insulation layer, a second insulation layer, a third insulation layer, a fourth insulation layer, and a fifth insulation layer stacked from bottom up in sequence. In the thin film transistor region, the glass substrate is provided with a light-shading metal member that is covered by the first insulation layer, the first insulation layer is provided with an active layer that is covered by the second insulation layer, two ends of the active layer are respectively connected with a source and a drain formed between the third insulation layer and the fourth insulation layer, the second insulation layer is provided with a gate that is covered by the third insulation layer, and the fourth insulation layer is provided with a common electrode that is covered by the fifth insulation layer. In the through-hole region, a pixel electrode is arranged on the fifth insulation layer and a through hole is configured in the fourth insulation layer, so that the pixel electrode is connected with the source or the drain after passing through the fifth insulation layer. A cushion layer is arranged under the through hole in an insulated manner.
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Patent Agency Ranking
公开(公告)号：US20170248828A1
公开(公告)日：2017-08-31
申请号：US14897664
申请日：2015-10-08
Inventor： Peng DU
IPC: G02F1/1362
CPC classification number: G02F1/136286 , G02F1/1362 , G09G3/3614 , G09G2300/0426 , G09G2300/0452 , G09G2330/021 , H01L27/124
Abstract: An array substrate includes a plurality of scanning lines, and a plurality of data lines. A plurality of regions is formed with the cooperation of the scanning lines and the data lines. Each region is provided with one pixel. The data lines are formed by branch lines of a plurality of data signal lines, and one data signal line forms two branch lines so as to drive two pixels in a same row of the array substrate. The two pixels are spaced from each other by an odd number of pixels. With respect to pixels in two adjacent rows, pixels in one row are all coupled with a data line on a left side, and pixels in the other row are all coupled with a data line on a right side, so that dot inversion of signal of pixels is realized when column inversion occurs to signal of data lines.
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公开(公告)号：US20170186398A1
公开(公告)日：2017-06-29
申请号：US14907827
申请日：2016-01-12
Inventor： Peng DU
CPC classification number: G09G5/003 , G09G3/20 , G09G2300/0408 , G09G2300/0426 , G09G2300/0809 , G09G2310/0251 , G09G2310/0267 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G09G2310/06 , G09G2310/08 , G09G2330/021 , H01L27/124 , H01L27/1255
Abstract: A GOA circuit located in a display panel is disclosed. The GOA circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a first boost thin film transistor, a second boost thin film transistor, a boost capacitor, a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, and a fifteenth thin film transistor. Through the first boost thin film transistor, the second boost thin film transistor, and the boost capacitor, a voltage level of a gate output signal outputted by a gate of the second thin film transistor is lifted.
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公开(公告)号：US20170186387A1
公开(公告)日：2017-06-29
申请号：US14907825
申请日：2016-01-11
Inventor： Xiaoxiao WANG , Peng DU
IPC: G09G3/36
CPC classification number: G09G3/3648 , G09G3/3677 , G09G2230/00 , G09G2300/0408 , G09G2300/0452 , G09G2310/0251 , G09G2310/0286 , G09G2320/0242 , G11C19/28
Abstract: A GOA (Gate driver On Array) for an LCD (Liquid Crystal Display) device is disclosed herein. The LCD device comprises a plurality of scanning lines. The GOA circuit comprises a plurality of GOA units, which are cascaded with each other as a plurality of level GOA units. The (n)th level GOA unit comprises a clock circuit, a pull-down circuit, a bootstrap capacitor circuit, a pull-up circuit, and a pull-down sustain circuit, to improve the color shift issue of a Tri-gate.
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公开(公告)号：US20170170203A1
公开(公告)日：2017-06-15
申请号：US14779089
申请日：2015-07-31
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Cong WANG , Peng DU , Xiaoxiao WANG
IPC: H01L27/12 , G02F1/1368 , H01L29/786
CPC classification number: H01L27/127 , G02F1/1368 , G02F2202/104 , H01L27/1222 , H01L27/1248 , H01L27/1288 , H01L29/78621 , H01L29/78675
Abstract: The present invention provides a LTPS array substrate and a manufacturing method thereof. The method comprises: forming a source electrode and a drain electrode on a substrate, forming polysilicon layers of a first region and a second region on the substrate including the source electrode and the drain electrode, and the thickness of the polysilicon layer of the first region is greater than the one of the second region, the polysilicon layer of the first region partially covers the source electrode and the drain electrode; passivating the surface of the polysilicon layer in order to turn the part of the adjacent surface of the polysilicon layer of the second region and the first region into an insulating layer; forming a gate electrode on the insulating layer between the source electrode and the drain electrode. The present invention can simplify the LTPS technical process and reduce the producing costs.
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公开(公告)号：US20170154588A1
公开(公告)日：2017-06-01
申请号：US14906560
申请日：2015-12-30
Inventor： Peng DU
IPC: G09G3/36
CPC classification number: G09G3/3614 , G09G3/3677 , G09G3/3688 , G09G2300/0426 , G09G2300/0452 , G09G2310/0224 , G09G2310/0251 , G09G2310/06 , G09G2330/021
Abstract: An array substrate for lowering switch frequency of drive polarity in data lines is described. The source driver charges a first sub-pixel group having the first polarity on pixel regions wherein the first sub-pixel group comprises a plurality of sub-pixels with the positive polarity disposed in the interlaced positions between data line and the scan lines. The source driver charges a second sub-pixel group having the second polarity on the pixel regions wherein the second sub-pixel group comprises a plurality of sub-pixels with the negative polarity disposed in the interlaced positions between data line and the scan lines. The first sub-pixel group is greater than each pixel region and the second sub-pixel group is greater than each pixel region so that either the switch frequency for driving the first sub-pixel group or the second sub-pixel group is lower than that of the two sub-pixels in the pixel region.
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