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公开(公告)号：US20230352101A1
公开(公告)日：2023-11-02
申请号：US18219083
申请日：2023-07-06
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G06F11/1068 , G11C29/52 , G06F11/1072 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G11C16/3427 , H03M13/152 , G11C2211/5644 , G11C2211/5648 , G11C16/0475
Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
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公开(公告)号：US11704234B2
公开(公告)日：2023-07-18
申请号：US16860093
申请日：2020-04-28
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang
CPC classification number: G06F12/0246 , G06F3/064 , G06F3/0608 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F9/4401 , G11C16/0483 , G11C16/08 , G11C16/28 , G06F2212/7201
Abstract: The present invention provides a method for accessing a flash memory module is disclosed, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of block, each block is implemented by a plurality of word lines, each word line corresponds to K pages, and each word line includes a plurality of memory cells supporting a plurality of states, and the method includes the steps of: receiving data from a host device; generating dummy data; and writing the data with the dummy data to a plurality of specific blocks, wherein for each of a portion of the word lines of the specific blocks, the dummy data is written into at least one of the K pages, and the data from the host device is written into the other page(s) of the K pages.
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公开(公告)号：US20230032032A1
公开(公告)日：2023-02-02
申请号：US17963999
申请日：2022-10-11
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu , Jian-Dong Du
Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
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公开(公告)号：US11494085B2
公开(公告)日：2022-11-08
申请号：US17367438
申请日：2021-07-05
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang
Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.
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公开(公告)号：US20220244886A1
公开(公告)日：2022-08-04
申请号：US17167099
申请日：2021-02-04
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang
Abstract: The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.
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Patent Agency Ranking
公开(公告)号：US20220066641A1
公开(公告)日：2022-03-03
申请号：US17500966
申请日：2021-10-14
Applicant: Silicon Motion, Inc.
Inventor： Jian-Dong Du , Chia-Jung Hsiao , Tsung-Chieh Yang
Abstract: A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.
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公开(公告)号：US11256425B2
公开(公告)日：2022-02-22
申请号：US16505701
申请日：2019-07-08
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang
Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method includes the steps of: sending a read command to the flash memory module to ask for data on at least one memory unit; receiving multi-bit information of a plurality of memory cells of the at least one memory unit from the flash memory module; and analyzing the multi-bit information of the plurality of memory cells to obtain a threshold voltage distribution of the plurality of memory cells for determining a decoding process.
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公开(公告)号：US20210334202A1
公开(公告)日：2021-10-28
申请号：US16860093
申请日：2020-04-28
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang
Abstract: The present invention provides a method for accessing a flash memory module is disclosed, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of block, each block is implemented by a plurality of word lines, each word line corresponds to K pages, and each word line includes a plurality of memory cells supporting a plurality of states, and the method includes the steps of: receiving data from a host device; generating dummy data; and writing the data with the dummy data to a plurality of specific blocks, wherein for each of a portion of the word lines of the specific blocks, the dummy data is written into at least one of the K pages, and the data from the host device is written into the other page(s) of the K pages.
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公开(公告)号：US20210334045A1
公开(公告)日：2021-10-28
申请号：US17367438
申请日：2021-07-05
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang
Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.
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公开(公告)号：US20210271402A1
公开(公告)日：2021-09-02
申请号：US17324121
申请日：2021-05-19
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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