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85 条记录 (耗时 0.026 秒)

    Apparatus and method for open loop buffer allocation
    54.
    发明申请
    Apparatus and method for open loop buffer allocation 审中-公开
    开环缓冲区分配的装置和方法

    公开(公告)号：US20050198459A1

    公开(公告)日：2005-09-08

    申请号：US10795037

    申请日：2004-03-04

    申请人： Zohar Bogin ,  Tuong Trieu ,  Sarath Kotamreddy ,  Jayesh Laddha

    发明人： Zohar Bogin ,  Tuong Trieu ,  Sarath Kotamreddy ,  Jayesh Laddha

    IPC分类号： G06F12/00

    CPC分类号： G06F5/06

    摘要： A method and apparatus for open loop buffer allocation. In one embodiment, the method includes loading requested data within a buffer according to a load rate. Concurrent with the loading of data within the buffer, the data is forwarded from the buffer according to drain rate. In situations where the load rate exceeds the drain rate, read requests may be throttled according to an approximate buffer capacity level to prohibit buffer overflow. In one embodiment, a rate for issuing data requests, for example, to memory, is regulated according to a predetermined buffer accumulation rate. Accordingly, in one embodiment, the open loop allocation scheme reduces latency while enabling sustained read streaming with a minimal size read buffer. Other embodiments are described and claimed.

    摘要翻译： 一种用于开环缓冲区分配的方法和装置。 在一个实施例中，该方法包括根据负载速率在缓冲器中加载所请求的数据。 与缓冲区内的数据加载一起，数据根据流失速率从缓冲区转发。 在负载率超过排放速率的情况下，读取请求可能会根据大约缓冲区容量限制，以禁止缓冲区溢出。 在一个实施例中，根据预定的缓冲器累积速率来调节用于发布数据请求（例如，存储器）的速率。 因此，在一个实施例中，开环分配方案减少等待时间，同时以最小尺寸的读缓冲器实现持续的读取流。 描述和要求保护其他实施例。

    Apparatus and a method to adjust signal timing on a memory interface
    55.
    发明申请
    Apparatus and a method to adjust signal timing on a memory interface 审中-公开
    用于调整存储器接口上的信号定时的装置和方法

    公开(公告)号：US20050190193A1

    公开(公告)日：2005-09-01

    申请号：US10791180

    申请日：2004-03-01

    申请人： David Freker ,  Zohar Bogin ,  Dour Navneet ,  Anoop Mukker ,  Tuong Trieu

    发明人： David Freker ,  Zohar Bogin ,  Dour Navneet ,  Anoop Mukker ,  Tuong Trieu

    IPC分类号： G06F13/00 ,  G06F13/16 ,  G06F13/372

    CPC分类号： G06F13/1689

    摘要： An apparatus and a method for adjusting signal timing in a memory interface have been disclosed. One embodiment of the apparatus includes a number of slave delay lock loops (DLLs) in a memory interface to adjust timing between a number of signals to compensate for timing skew, and a number of input/output (I/O) buffers to output the adjusted signals to one or more memory devices coupled to the memory interface. Other embodiments are described and claimed.

    摘要翻译： 已经公开了一种用于调整存储器接口中的信号定时的装置和方法。 该装置的一个实施例包括在存储器接口中的多个从属延迟锁定环（DLL），用于调整多个信号之间的定时以补偿定时偏差，以及多个输入/输出（I / O）缓冲器，以输出 调整的信号到耦合到存储器接口的一个或多个存储器件。 描述和要求保护其他实施例。

    Hardware detected command-per-clock
    57.
    发明申请
    Hardware detected command-per-clock 失效
    硬件检测每个时钟指令

    公开(公告)号：US20050144374A1

    公开(公告)日：2005-06-30

    申请号：US10749183

    申请日：2003-12-30

    申请人： Suryaprasad Karecnahalli ,  Zohar Bogin ,  Anoop Mukker

    发明人： Suryaprasad Karecnahalli ,  Zohar Bogin ,  Anoop Mukker

    IPC分类号： G06F12/00 ,  G06F13/16

    CPC分类号： G06F13/1631

    摘要： A memory controller is coupled to a memory device via a memory channel. The memory controller includes a command-per-clock detection unit that compares a portion of a current address with a portion of a previous address. If there is a match, then the memory controller can continue to assert a chip select line coupled to the memory device. The command-per-clock detection unit checks to see whether only certain low-order bits of the address lines are toggling between the current and previous addresses. Additional copies of address lines for particular low-order bits are provided to the memory device to reduce loading on the low order bit address lines, allowing the low order bit address lines to toggle quickly in order to avoid the necessity of inserting a one clock period wait state. If the command-per-clock detection unit does not find a match (meaning that more than the low order address bits are toggling) then the wait state is inserted by deasserting the chip select line for a clock period.

    摘要翻译： 存储器控制器经由存储器通道耦合到存储器件。 存储器控制器包括每时钟脉冲检测单元，其将当前地址的一部分与先前地址的一部分进行比较。 如果存在匹配，则存储器控制器可以继续断言耦合到存储器件的芯片选择线。 命令/时钟检测单元检查地址线的某些低位是否在当前地址和以前的地址之间切换。 用于特定低位的地址线的附加副本被提供给存储器件以减少低位位地址线上的负载，允许低位位地址线快速切换，以避免插入一个时钟周期 等待状态 如果命令/时钟检测单元没有找到匹配（意味着比低位地址位多于切换），则通过在芯片选择线上断开时钟周期来插入等待状态。

    Managing bus transaction dependencies
    58.
    发明授权
    Managing bus transaction dependencies 失效

    公开(公告)号：US06694390B1

    公开(公告)日：2004-02-17

    申请号：US09659108

    申请日：2000-09-11

    申请人： Zohar Bogin ,  Serafin E. Garcia

    发明人： Zohar Bogin ,  Serafin E. Garcia

    IPC分类号： G06F300

    CPC分类号： G06F13/24 ,  G06F13/385

    摘要： A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.

    Method and apparatus for write cache flush and fill mechanisms
    59.
    发明授权
    Method and apparatus for write cache flush and fill mechanisms 有权
    写缓存清理和填充机制的方法和装置

    公开(公告)号：US06658533B1

    公开(公告)日：2003-12-02

    申请号：US09667405

    申请日：2000-09-21

    申请人： Zohar Bogin ,  Steven J. Clohset

    发明人： Zohar Bogin ,  Steven J. Clohset

    IPC分类号： G06F1200

    CPC分类号： G06F12/0804 ,  G06F12/0897 ,  G06F2212/304

    摘要： A write cache that reduces the number of memory accesses required to write data to main memory. When a memory write request is executed, the request not only updates the relevant location in cache memory, but the request is also directed to updating the corresponding location in main memory. A separate write cache is dedicated to temporarily holding multiple write requests so that they can be organized for more efficient transmission to memory in burst transfers. In one embodiment, all writes within a predefined range of addresses can be written to memory as a group. In another embodiment, entries are held in the write cache until a minimum number of entries are available for writing to memory, and a least-recently-used mechanism can be used to decide which entries to transmit first. In yet another embodiment, partial writes are merged into a single cache line, to be written to memory in a single burst transmission.

    摘要翻译： 写缓存，减少将数据写入主内存所需的内存访问次数。 当执行存储器写入请求时，请求不仅更新高速缓冲存储器中的相关位置，而且还要求更新主存储器中的对应位置。 单独的写高速缓存专用于临时保存多个写请求，使得它们可以被组织以在突发传输中更有效地传输到存储器。 在一个实施例中，预定义地址范围内的所有写入可以作为一组写入存储器。 在另一个实施例中，条目被保留在写高速缓存中，直到最少数目的条目可用于写入存储器，并且最近最少使用的机制可以用于决定首先发送哪些条目。 在另一个实施例中，部分写入被合并到单个高速缓存行中，以单个突发传输方式写入存储器。

    Inserting bus inversion scheme in bus path without increased access latency
    60.
    发明授权
    Inserting bus inversion scheme in bus path without increased access latency 失效
    在总线路径中插入总线反演方案，而不增加访问延迟

    公开(公告)号：US06584526B1

    公开(公告)日：2003-06-24

    申请号：US09667049

    申请日：2000-09-21

    申请人： Zohar Bogin ,  Serafin E. Garcia ,  Steven J. Clohset

    发明人： Zohar Bogin ,  Serafin E. Garcia ,  Steven J. Clohset

    IPC分类号： G06F1338

    CPC分类号： G06F11/10 ,  G06F13/4213 ,  G11C7/1078 ,  G11C7/1084

    摘要： A technique to reduce accumulated latencies in bus transmission time when a bus inversion scheme is employed. The bus inversion scheme inverts all the data bits whenever more than one-half of the data bits are active, so that the bus never has more that one-half of the bits active during a data transfer. This minimizes the number of driver circuits that are actively driving the bus at any given time. Since it takes a certain amount to time to determine if more than one-half of the bits are active, this process can add to overall latency, or data transfer time on the bus. By placing the bus inversion function in parallel with another function that also contributes to bus latency, such as error correction code (ECC) calculation, only the more time-consuming of the two functions will increase bus latency.

    摘要翻译： 一种在采用总线反转方案时减少总线传输时间的累积延迟的技术。 每当超过一半的数据位有效时，总线反相方案会反转所有数据位，这样在数据传输过程中，总线从不会有更多的一半位有效。 这样可以最大限度地减少任何给定时间内积极驱动总线的驱动电路的数量。 由于需要一定的时间来确定是否有超过一半的位是活动的，所以该过程可以增加总线上的总延迟或数据传输时间。 通过将总线反转功能与还有助于总线等待时间（如纠错码（ECC））计算的另一个功能并行布置，只有更多的时间消耗这两个功能才能增加总线延迟。