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    Non-collinear end-to-end structures with sub-resolution assist features
    56.
    发明授权
    Non-collinear end-to-end structures with sub-resolution assist features 失效
    具有次分辨率辅助功能的非共线端对端结构

    公开(公告)号：US07572557B2

    公开(公告)日：2009-08-11

    申请号：US11297209

    申请日：2005-12-07

    Applicant: Charles H. Wallace ,  Shannon E. Daviess ,  Swaminathan Sivakumar

    Inventor： Charles H. Wallace ,  Shannon E. Daviess ,  Swaminathan Sivakumar

    IPC: G03F1/00 ,  H01L21/00 ,  G06F17/50

    CPC classification number: G03F1/36

    Abstract: Sub-resolution assist features for non-collinear features are described for use in photolithography. A photolithography mask with elongated features is synthesized. An end-to-end gap between two features if found for which the ends of the two features facing the gap are linearly offset from one another. A sub-resolution assist feature is applied to the end-to-end gap between the elongated features, and the synthesized photolithography mask is modified to include the sub-resolution assist feature.

    Abstract translation: 描述了非共线特征的子分辨率辅助功能，用于光刻。 合成具有细长特征的光刻掩模。 如果发现两个特征面对间隙的两端的端部彼此线性偏移，则两个特征之间的端对端间隙。 子分辨率辅助特征被应用于细长特征之间的端到端间隙，并且合成的光刻掩模被修改为包括子分辨率辅助特征。

    Transistor Having Raised Source/Drain Self-Aligned Contacts And Method Of Forming Same
    57.
    发明申请
    Transistor Having Raised Source/Drain Self-Aligned Contacts And Method Of Forming Same 有权
    晶体管上升源/排水自对准触点及其形成方法

    公开(公告)号：US20090166759A1

    公开(公告)日：2009-07-02

    申请号：US11965850

    申请日：2007-12-28

    Applicant: Swaminathan Sivakumar

    Inventor： Swaminathan Sivakumar

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L21/76897 ,  H01L29/66628 ,  H01L29/66659

    Abstract: A transistor structure and a method of forming same. The transistor structure includes: a semiconductor substrate having a gate-side surface; a gate disposed on the gate-side surface, the gate extending above the gate-side surface by a first height; a semiconductor extension disposed on the gate-side surface and extending above the gate-side surface by a second height larger than the first height, the semiconductor extension including a diffusion region having a diffusion surface located at the second height; and a diffusion contact element electrically coupled to the diffusion surface.

    Abstract translation: 晶体管结构及其形成方法。 晶体管结构包括：具有栅极侧表面的半导体衬底; 设置在所述栅极侧表面上的栅极，所述栅极在所述栅极侧表面上延伸第一高度; 半导体延伸部，其设置在所述栅极侧表面上并且在所述栅极侧表面上方延伸高于所述第一高度的第二高度，所述半导体延伸部包括具有位于所述第二高度的扩散表面的扩散区域; 以及电耦合到扩散表面的扩散接触元件。

    Pre-exposure of patterned photoresist films to achieve critical dimension reduction during temperature reflow
    58.
    发明授权
    Pre-exposure of patterned photoresist films to achieve critical dimension reduction during temperature reflow 有权
    图案化的光致抗蚀剂膜的预曝光以在温度回流期间实现临界尺寸减小

    公开(公告)号：US07258965B2

    公开(公告)日：2007-08-21

    申请号：US10750053

    申请日：2003-12-30

    Applicant: Rex K. Frost ,  Swaminathan Sivakumar

    Inventor： Rex K. Frost ,  Swaminathan Sivakumar

    IPC: G03F7/26

    CPC classification number: G03F7/40

    Abstract: The present invention relates to the reduction of critical dimensions and the reduction of feature sizes in manufacturing integrated circuits. Specifically, the method controls photoresist flow rates to develop critical dimensions beyond the resolution limits of the photoresist material used, and the limits of lithographic tool sets. The resist material characteristics are modified by exposing the resist pattern to either electrons, photons, or ions. The exposure modifies the glass transition temperature, cross linking characteristics, decomposition temperature, or molecular weight of the resist material. The post-exposure resist is then easier to control during a subsequent reflow process to reduce the hole size or line size of the patterned resist.

    Abstract translation: 本发明涉及减小制造集成电路中的关键尺寸和减小特征尺寸。 具体地说，该方法控制光致抗蚀剂的流速，以发展超出所使用的光致抗蚀剂材料的分辨率极限以及光刻工具组的极限的关键尺寸。 通过将抗蚀剂图案暴露于电子，光子或离子来修饰抗蚀剂材料特性。 曝光改变抗蚀剂材料的玻璃化转变温度，交联特性，分解温度或分子量。 在后续回流工艺中，后曝光抗蚀剂更容易控制，以减小图案化抗蚀剂的孔尺寸或线尺寸。

    Multiple exposure and shrink to achieve reduced dimensions
    60.
    发明申请
    Multiple exposure and shrink to achieve reduced dimensions 审中-公开
    多次曝光和收缩以实现尺寸减小

    公开(公告)号：US20050255411A1

    公开(公告)日：2005-11-17

    申请号：US10846616

    申请日：2004-05-14

    Applicant: Rex Frost ,  Swaminathan Sivakumar

    Inventor： Rex Frost ,  Swaminathan Sivakumar

    IPC: G03F7/00 ,  G03F7/40

    CPC classification number: G03F7/40 ,  G03F7/0035

    Abstract: The embodiments of the present invention include decomposing a pattern into dependent patterns. The dependent patterns may then be transferred to a semiconductor wafer surface and the pattern's features may be shrunk. The shrunk features may be transferred to the substrate. The multiple exposures and shrinks facilitate smaller feature dimensions.

    Abstract translation: 本发明的实施例包括将图案分解为依赖图案。 然后可以将依赖图案转移到半导体晶片表面，并且图案的特征可能会收缩。 缩小的特征可以转移到基底。 多次曝光和收缩有助于缩小特征尺寸。

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