公开(公告)号：US20150179613A1

公开(公告)日：2015-06-25

申请号：US14135153

申请日：2013-12-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu-Ting Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Chia-Chieh Lin ,  U-Ting Chen

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L25/0657 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/80896 ,  H01L2224/82106 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00 ,  H05K3/467 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

摘要翻译： 提供了互连装置和形成互连装置的方法。 两个集成电路结合在一起。 通过一个基板形成第一开口。 沿着第一开口的侧壁和底部形成多层电介质膜。 形成从第一开口延伸到集成电路中的焊盘的第二开口。 形成电介质衬垫，并且用导电材料填充开口以形成导电插塞。

公开(公告)号：US20150179612A1

公开(公告)日：2015-06-25

申请号：US14135103

申请日：2013-12-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu-Ting Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  U-Ting Chen ,  Shih Pei Chou

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/91 ,  H01L25/50 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/12036 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/82 ,  H01L2224/8203

摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

摘要翻译： 提供了互连装置和形成互连装置的方法。 两个集成电路结合在一起。 通过一个基板形成第一开口。 沿第一开口的侧壁形成多层电介质膜。 一个或多个蚀刻工艺沿着第一开口的侧壁形成一个或多个间隔物结构。 形成从第一开口延伸到集成电路中的焊盘的第二开口。 形成电介质衬垫，并且用导电材料填充开口以形成导电插塞。

公开(公告)号：US20150118787A1

公开(公告)日：2015-04-30

申请号：US14560676

申请日：2014-12-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Shin Chu ,  Cheng-Tao Lin ,  Meng-Hsun Wan ,  Szu-Ying Chen ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC分类号： H01L27/146

CPC分类号： H01L27/14689 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14665 ,  H01L27/14692 ,  H01L27/301 ,  H01L27/307

摘要： A device includes a plurality of isolation spacers, and a plurality of bottom electrodes, wherein adjacent ones of the plurality of bottom electrodes are insulated from each other by respective ones of the plurality of isolation spacers. A plurality of photoelectrical conversion regions overlaps the plurality of bottom electrodes, wherein adjacent ones of the plurality of photoelectrical conversion regions are insulated from each other by respective ones of the plurality of isolation spacers. A top electrode overlies the plurality of photoelectrical conversion regions and the plurality of isolation spacers.

摘要翻译： 一种器件包括多个隔离隔离物和多个底部电极，其中多个底部电极中的相邻的底部电极通过多个隔离间隔物中的相应隔离间隔彼此绝缘。 多个光电转换区域与多个底部电极重叠，其中多个光电转换区域中的相邻光电转换区域通过多个隔离间隔物中的相应隔离间隔彼此绝缘。 顶部电极覆盖多个光电转换区域和多个隔离间隔物。

公开(公告)号：US20150079718A1

公开(公告)日：2015-03-19

申请号：US14550410

申请日：2014-11-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Szu-Ying Chen ,  Meng-Hsun Wan ,  Tzu-Jui Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu

IPC分类号： H01L25/00 ,  H01L21/768 ,  H01L27/146 ,  H01L25/18

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L25/18 ,  H01L27/14609 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14685 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a first chip including an image sensor therein, and a second chip bonded to the first chip. The second chip includes a logic device selected from the group consisting essentially of a reset transistor, a selector, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit.

摘要翻译： 一种器件包括其中包括图像传感器的第一芯片和与第一芯片接合的第二芯片。 第二芯片包括从基本上由复位晶体管，选择器，行选择器及其组合组成的组中选择的逻辑器件。 逻辑器件和图像传感器彼此电耦合，并且是相同像素单元的部分。

公开(公告)号：US20150064832A1

公开(公告)日：2015-03-05

申请号：US14531820

申请日：2014-11-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Hsun Wan ,  Yi-Shin Chu ,  Szu-Ying Chen ,  Pao-Tung Chen ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC分类号： H01L27/146 ,  H01L31/0352 ,  H01L31/18

CPC分类号： H01L27/14632 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/1469 ,  H01L31/022466 ,  H01L31/035218 ,  H01L31/03762 ,  H01L31/18 ,  H04N5/378

摘要： A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.

公开(公告)号：US08969991B2

公开(公告)日：2015-03-03

申请号：US14178084

申请日：2014-02-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Keng-Yu Chou ,  Shuang-Ji Tsai ,  Min-Feng Kao

IPC分类号： H01L21/00 ,  H01L27/146 ,  H01L31/0216 ,  H01L31/18

CPC分类号： H01L27/14685 ,  G02B1/11 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L31/02161 ,  H01L31/1868 ,  Y02E10/50 ,  Y02P70/521

摘要： BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.

摘要翻译： BSI图像传感器和方法。 在一个实施例中，提供具有传感器阵列和周边区域并具有前侧和后侧表面的基板; 底部抗反射涂层（BARC）在传感器阵列区域和外围区域的上方形成在第一厚度的背侧上; 在BARC上形成第一介电层; 形成金属屏蔽; 从所述传感器阵列区域上方选择性地去除所述金属屏蔽件; 从所述传感器阵列区域上方选择性地去除所述第一介电层，其中所述BARC的第一厚度的一部分也被去除，并且在选择性地去除所述第一介电层的过程中所述BARC的第一厚度的剩余部分保留; 在BARC的其余部分和金属屏蔽层之上形成第二电介质层; 以及在所述第二介电层上形成钝化层。

公开(公告)号：US08900966B2

公开(公告)日：2014-12-02

申请号：US14044716

申请日：2013-10-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jen-Cheng Liu ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

IPC分类号： H01L23/544 ,  H01L21/71

CPC分类号： H01L23/544 ,  H01L21/71 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

摘要翻译： 提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

公开(公告)号：US20140308772A1

公开(公告)日：2014-10-16

申请号：US14281271

申请日：2014-05-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jeng-Shyan Lin ,  Feng-Chi Hung ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Szu-Ying Chen ,  Wen-De Wang ,  Tzu-Hsuan Hsu

IPC分类号： H01L27/146

CPC分类号： H01L27/14687 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/1469 ,  H01L2224/48463

摘要： A method includes bonding a Backside Illumination (BSI) image sensor chip to a device chip, forming a first via in the BSI image sensor chip to connect to a first integrated circuit device in the BSI image sensor chip, forming a second via penetrating through the BSI image sensor chip to connect to a second integrated circuit device in the device chip, and forming a metal pad to connect the first via to the second via.

摘要翻译： 一种方法包括将背面照明（BSI）图像传感器芯片接合到器件芯片，在BSI图像传感器芯片中形成第一通孔，以连接到BSI图像传感器芯片中的第一集成电路器件，形成穿过 BSI图像传感器芯片，用于连接到器件芯片中的第二集成电路器件，并形成金属焊盘以将第一通孔连接到第二通孔。

公开(公告)号：US20140264929A1

公开(公告)日：2014-09-18

申请号：US13937055

申请日：2013-07-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Ting Tsai ,  Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Chih-Hui Huang ,  Sheng-Chau Chen ,  Shih-Pei Chou ,  Chia-Chieh Lin

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76898 ,  H01L21/76805 ,  H01L23/481 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12036 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2224/80 ,  H01L2924/00 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

摘要翻译： 公开了一种堆叠集成电路（IC）装置和方法。 堆叠式IC器件包括第一半导体元件。 第一衬底包括在第一衬底中的介质块; 以及形成在第一衬底上的第一金属间介电层中的多个第一导电特征。 堆叠式IC器件还包括接合在第一半导体元件上的第二半导体元件。 第二半导体元件包括第二基板和形成在第二基板上的第二金属间介电层中的多个第二导电特征。 叠置的IC器件还包括耦合在第一导电特征和第二导电特征之间的导电深互连插塞。 导电深互连插头由绝缘块，第一金属间介质层和第二金属间介质层隔离。

公开(公告)号：US20140264883A1

公开(公告)日：2014-09-18

申请号：US13866802

申请日：2013-04-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu-Ting Tsai ,  Jeng-Shyan Lin ,  Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung

IPC分类号： H01L23/522 ,  H01L23/532

CPC分类号： A61N1/3931 ,  A61N1/3987 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53257 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2224/08145 ,  H01L2224/80894 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.

摘要翻译： 半导体器件包括结合在第二芯片上的第一芯片。 第一芯片包括形成在第一IMD层中的第一衬底和第一互连部件。 第二芯片包括形成在第二IMD层中的第二基板和第二互连部件。 该装置还包括形成在第一衬底和第一IMD层内的第一导电插塞，其中第一导电插塞耦合到第一互连部件和通过第一衬底和第一IMD层形成的第二导电插塞，并且部分地穿过 所述第二IMD层，其中所述第二导电插塞耦合到第二互连部件。