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51.发明申请公开(公告)号：US20150019896A1
公开(公告)日：2015-01-15
申请号：US14326928
申请日：2014-07-09
Applicant: Texas Instruments Incorporated
Inventor： Timothy David Anderson , Duc Quang Bui
CPC classification number: G06F9/30036 , G06F1/3206 , G06F1/3287 , G06F9/30014 , G06F9/30018 , G06F9/30072 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3887 , Y02D10/171
Abstract: The vector data path is divided into smaller vector lanes. The number of active vector lanes is controllable on the fly by the programmer to match the requirements of the executing program, and inactive vector lanes are powered down by the CPU to increase power efficiency of the vector processor.
Abstract translation: 矢量数据路径分为较小的矢量通道。 活动矢量通道的数量可由程序员在飞行中控制以匹配执行程序的要求，并且CPU的无源向量通道由CPU掉电以提高向量处理器的功率效率。
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公开(公告)号：US20150019838A1
公开(公告)日：2015-01-15
申请号：US14326943
申请日：2014-07-09
Applicant: Texas Instruments Incorporated
Inventor： Timothy David Anderson , Duc Quang Bui , Peter Richard Dent
Abstract: A method of loading and duplicating scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.
Abstract translation: 将标量数据从源加载和复制到目标寄存器的方法。 根据复制模式，数据可以以字节，半字，字或双字部分复制。
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公开(公告)号：US12217054B2
公开(公告)日：2025-02-04
申请号：US17946113
申请日：2022-09-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.
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公开(公告)号：US12099843B2
公开(公告)日：2024-09-24
申请号：US18120601
申请日：2023-03-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Timothy David Anderson , Duc Quang Bui , Joseph Zbiciak , Sahithi Krishna , Soujanya Narnur
IPC: G06F9/30 , G06F12/0811
CPC classification number: G06F9/3016 , G06F9/30065 , G06F9/30098 , G06F12/0811
Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.
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公开(公告)号：US20240248714A1
公开(公告)日：2024-07-25
申请号：US18625645
申请日：2024-04-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Timothy David Anderson , Duc Quang Bui
IPC: G06F9/30 , G06F1/3206 , G06F1/3287 , G06F9/38
CPC classification number: G06F9/30036 , G06F1/3206 , G06F1/3287 , G06F9/30014 , G06F9/30018 , G06F9/30072 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/3887 , Y02D10/00
Abstract: In an embodiment, a circuit includes a data path including at least a first lane of a first width and a second lane of a second, larger, width; an execution unit to execute a first instruction on data of the first width or less using the first lane, and to execute a second instruction on data greater than the first width and less than or equal to the second width using the second lane; and a control register that stores a value indicating which of the first and second lanes to be used in instruction execution by the execution unit. The circuit is configured to, based on the value stored in the control register, power off the first lane when the execution unit executes the second instruction but not the first instruction, and power off the second lane when the execution unit executes the first instruction but not the second instruction.
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Patent Agency Ranking
56.发明公开公开(公告)号：US20240220263A1
公开(公告)日：2024-07-04
申请号：US18609622
申请日：2024-03-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: G06F9/3802 , G06F9/30072 , G06F9/30076 , G06F9/3013 , G06F9/30145 , G06F9/30185 , G06F9/3822 , G06F9/3853 , G06F9/3891
Abstract: In an example, a device includes a register file; a set of functional units coupled to the register file; and an instruction decoder coupled to the register file and to the set of functional units. The instruction decoder receives an executable instruction directed to a specific functional unit of the set of functional unit. The executable instruction includes a segment specifying a register of the register file. The instruction decoder also provides the executable instruction to the specific functional unit. The specific functional unit then determines whether to execute the executable instruction based on a value stored in the register of the register file specified by the segment of the executable instruction.
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公开(公告)号：US11748270B2
公开(公告)日：2023-09-05
申请号：US17990812
申请日：2022-11-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Duc Quang Bui , Joseph Raymond Michael Zbiciak
IPC: G06F9/30 , G06F12/1045 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/48 , G06F17/16 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009
CPC classification number: G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/3016 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3818 , G06F9/3836 , G06F9/3851 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , G06F9/3822 , G06F11/10 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
Abstract: In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.
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公开(公告)号：US11507520B2
公开(公告)日：2022-11-22
申请号：US17187984
申请日：2021-03-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Duc Quang Bui , Joseph Raymond Michael Zbiciak
IPC: G06F9/30 , G06F12/1045 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/48 , G06F17/16 , H03H17/06 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009 , G06F15/78
Abstract: In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.
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公开(公告)号：US11449336B2
公开(公告)日：2022-09-20
申请号：US16786457
申请日：2020-02-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.
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公开(公告)号：US20210344361A1
公开(公告)日：2021-11-04
申请号：US17378886
申请日：2021-07-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Dheera Balasubramanian , Joseph Zbiciak , Duc Quang Bui , Timothy David Anderson
Abstract: A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits.
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