公开(公告)号：US09305852B1

公开(公告)日：2016-04-05

申请号：US14537943

申请日：2014-11-11

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L23/48 ,  H01L23/06 ,  H01L25/18 ,  H01L25/00 ,  H01L23/053 ,  H01L21/52 ,  H01L23/00 ,  H01L21/82 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/074 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/06181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/83851 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/00 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1037 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15156 ,  H01L2924/157 ,  H01L2224/83

Abstract: An electronic system comprises a first chip (101) of single-crystalline semiconductor including a first electronic device embedded in a second chip (102) of single-crystalline semiconductor shaped as a container having a slab (104) bordered by ridges (103), and including a second electronic device. The nested chips are assembled in a container of low-grade silicon shaped as a slab 130 bordered by retaining walls 131 and including conductive traces and terminals. The first electronic device is connected to the second electronic device by attaching the first chip onto the slab of the second chip; and the first and second electronic devices are connected to the container by embedding the second chip in the container, wherein the nested first and second chips operate as an electronic system and the container operates as the package of the system. For first and second devices as field effect transistors, the system is a power block.

Abstract translation: 电子系统包括单晶半导体的第一芯片（101），其包括第一电子器件，该第一电子器件嵌入单晶半导体的第二芯片（102）中，所述第一芯片形成为具有由脊（103）界定的板（104）的容器， 并且包括第二电子设备。 嵌套芯片组装在低档硅片的容器中，该容器由板状物130与挡板壁131相邻并且包括导电迹线和端子。 第一电子设备通过将第一芯片附接到第二芯片的板上而连接到第二电子设备; 并且第一和第二电子设备通过将第二芯片嵌入容器而连接到容器，其中嵌套的第一和第二芯片作为电子系统操作，并且容器作为系统的封装进行操作。 对于作为场效应晶体管的第一和第二器件，该系统是功率块。

公开(公告)号：US09299830B1

公开(公告)日：2016-03-29

申请号：US14706927

申请日：2015-05-07

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Seetharaman Sridhar ,  Christopher Boguslaw Kocon ,  Simon John Molloy ,  Hong Yang

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L21/28114 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66734

Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

Abstract translation: 半导体器件包含垂直MOS晶体管，其沟槽中的沟槽栅极延伸穿过垂直漂移区到漏极区。 这些沟槽在门下有现场板; 场板与漂移区相邻并且具有多个段。 将场板与漂移区分离的沟槽中的电介质衬垫的厚度大于门和主体之间的栅极电介质层。 电介质衬垫在沟槽底部的场板的下段上比在栅极正下方的上段更厚。 沟槽栅极可以与场板电隔离，或者可以连接到上部段。 场板的段可以彼此电隔离或者可以在沟槽中彼此连接。

公开(公告)号：US09245994B2

公开(公告)日：2016-01-26

申请号：US14175456

申请日：2014-02-07

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson

IPC: H01L29/78 ,  H01L29/40

CPC classification number: H01L29/7811 ,  H01L29/407

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) in and on a semiconductor surface provides a drift region of a first conductivity type. A plurality of active area trenches in the drift region, and first and second termination trenches are each parallel to and together sandwiching the active area trenches. The active area trenches and termination trenches include a trench dielectric liner and electrically conductive filler material filled field plates. A gate is over the drain drift region between active area trenches. A body region of a second conductivity abuts the active region trenches. A source of the first conductivity type is in the body region on opposing sides of the gate. A vertical drain drift region uses the drift region below the body region. A first and second curved trench feature couples the field plate of the first and second termination trench to field plates of active area trenches.

Abstract translation: 半导体表面中和之上的金属氧化物半导体场效应晶体管（MOSFET）提供第一导电类型的漂移区域。 漂移区域中的多个有源区沟槽以及第一和第二端接沟槽各自平行并夹在有源区沟槽中。 有源区沟槽和终端沟槽包括沟槽电介质衬垫和填充有导电填料的场板。 栅极位于有源区沟槽之间的漏极漂移区域之上。 第二导电体的主体区域邻接有源区沟槽。 第一导电类型的源在门的相对侧上的体区中。 垂直漏极漂移区域使用身体区域下方的漂移区域。 第一和第二弯曲沟槽特征将第一和第二端接沟槽的场板与有源区沟槽的场板耦合。