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    Processing device with nonvolatile logic array backup
    55.
    发明授权
    Processing device with nonvolatile logic array backup 有权

    公开(公告)号：US10102889B2

    公开(公告)日：2018-10-16

    申请号：US13770304

    申请日：2013-02-19

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G11C7/22 ,  G06F3/06 ,  H03K3/3562 ,  G06F12/02 ,  G06F9/4401 ,  G06F1/32 ,  G06F13/00 ,  G06F11/14 ,  G06F11/10 ,  G11C14/00

    Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

    Compute Through Power Loss Approach For Processing Device Having Nonvolatile Logic Memory
    58.
    发明申请
    Compute Through Power Loss Approach For Processing Device Having Nonvolatile Logic Memory 审中-公开
    通过功率损耗方法计算具有非易失性逻辑存储器的处理器件

    公开(公告)号：US20160246355A1

    公开(公告)日：2016-08-25

    申请号：US14918133

    申请日：2015-10-20

    Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland GmbH

    Inventor： Andreas Dannenberg ,  Brent Peterson ,  Aik K. Goh ,  Joerg Schreiner ,  Michael Zwerg ,  Steven Craig Bartling

    IPC: G06F1/32 ,  G06F9/44 ,  G06F12/02

    CPC classification number: G06F1/3275 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4418 ,  G06F12/0246 ,  G06F2212/7203 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/44 ,  Y02D50/20

    Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a software routine configured to be run by the CPU that effects saving to a non-volatile memory a state of the CPU and/or the device's peripherals before entering the deep low-power mode. The software routine can be configured to control this state storage in response to detecting a low power event, i.e., loss of power sufficient to run the CPU, or a software command to enter the deep low power mode to save power as part of an efficiency program. Then, upon wake up from the deep low power mode, the software routine is first run by the CPU to effect restoring from the non-volatile memory the state of the CPU and the peripherals before execution of a primary application for the central processing unit.

    Abstract translation: 计算设备装置有助于使用深度低功率模式，其包括通过包括被配置为由CPU运行的软件例程来关闭设备的CPU，该软件程序将CPU和/或设备的状态保存到非易失性存储器 外设进入深低功耗模式。 响应于检测到低功率事件（即，足够运行CPU的功率损失）或软件命令进入深低功率模式以节省功率作为效率的一部分，可以配置软件例程来控制该状态存储 程序。 然后，从深度低功耗模式唤醒时，软件程序首先由CPU执行，以在执行中央处理单元的主应用程序之前从非易失性存储器恢复CPU和外围设备的状态。

    Nonvolatile logic array and power domain segmentation in processing device
    59.
    发明授权
    Nonvolatile logic array and power domain segmentation in processing device 有权
    非易失性逻辑阵列和功率域分割处理器件

    公开(公告)号：US09342259B2

    公开(公告)日：2016-05-17

    申请号：US13770498

    申请日：2013-02-19

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F1/00 ,  G06F3/06 ,  G06F12/02 ,  G06F9/44 ,  G06F1/32 ,  G06F13/00 ,  G06F11/14 ,  G06F11/10

    CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device.

    Abstract translation: 计算设备包括与第一功能相关联的第一组非易失性逻辑元件阵列和与第二功能相关联的第二组非易失性逻辑元件阵列。 第一组和第二组非易失性逻辑元件阵列是独立可控的。 第一电源域向计算设备的交换逻辑元件供电，第二电源域为配置成控制用于将数据存储到非易失性逻辑单元阵列或从非易失性逻辑单元阵列读取数据的信号的逻辑元件供电，而第三电源域供电 用于非易失性逻辑元件阵列。 基于系统状态，不同的电源域被独立上电或下电，以减少在冗余逻辑切换期间的功率损耗以及在恢复系统状态期间伴随的寄生功率消耗，并且在计算的常规操作期间减少备用存储元件的功率泄漏 设备。

    Nonvolatile logic array with retention flip flops to reduce switching power during wakeup
    60.
    发明授权
    Nonvolatile logic array with retention flip flops to reduce switching power during wakeup 有权
    具有保持触发器的非易失性逻辑阵列，以降低唤醒期间的开关电源

    公开(公告)号：US09058126B2

    公开(公告)日：2015-06-16

    申请号：US13770368

    申请日：2013-02-19

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F12/10 ,  G06F3/06 ,  G06F12/02 ,  G06F9/44 ,  G06F1/32 ,  G06F13/00 ,  G06F11/14

    CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A processing device is operated using a plurality of volatile storage elements. Data in the plurality of volatile storage elements is stored in a plurality of non-volatile logic element arrays. A primary logic circuit portion of individual ones of the plurality of volatile storage elements is powered by a first power domain, and a slave stage circuit portion of individual ones of the plurality of volatile storage elements is powered by a second power domain. During a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the first power domain is powered down and the second power domain is maintained. In a further approach, the plurality of non-volatile logic element arrays is powered by a third power domain, which is powered down during regular operation of the processing device.

    Abstract translation: 使用多个易失性存储元件来操作处理装置。 多个易失性存储元件中的数据被存储在多个非易失性逻辑元件阵列中。 多个易失性存储元件中的各个易失性存储元件的主要逻辑电路部分由第一电源域供电，并且多个易失性存储元件中的单个的易失性存储元件的从属级电路部分由第二电源域供电。 在从多个非易失性逻辑单元阵列向多个易失性存储元件的数据写回期间，第一功率域被断电并维持第二功率域。 在另一种方法中，多个非易失性逻辑单元阵列由第三功率域供电，该第三功率域在处理设备的常规操作期间被关断。

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