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    Semiconductor integrated circuit and driving method using comparator feedback loop to switch subtraction bypass circuit
    51.
    发明授权
    Semiconductor integrated circuit and driving method using comparator feedback loop to switch subtraction bypass circuit 失效
    半导体集成电路和驱动方法使用比较器反馈回路来切换减法旁路电路

    公开(公告)号：US06259393B1

    公开(公告)日：2001-07-10

    申请号：US09105258

    申请日：1998-06-26

    申请人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

    发明人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

    IPC分类号： H03M138

    CPC分类号： H03M1/403

    摘要： In order to solve the problem of increase in circuit scale and increase in power consumption due to use of a DA converter, a semiconductor integrated circuit comprises a signal amplifier 2, 10 capable of switching of a gain to 1 or 2, an arithmetic processor 7, 9 for performing a subtraction process of a reference voltage from an input signal to output a result thereof or for outputting the input signal without performing the subtraction process, a switch 8 whose one switch terminal is connected to a signal input terminal, whose other switch terminal is connected to an output side of sample hold circuits 5, 6, and whose common terminal is connected to an input side of the arithmetic processor, a comparator 3 for comparing an output from the signal amplifier with the reference voltage to binarize the output, and a switch 11 for connecting an output side of the signal amplifier to an input side of the sample hold circuits, wherein the arithmetic processor carries out a changeover between the operation of performing the subtraction process of the reference voltage from the input signal to output the result and the operation of outputting the input signal without performing the subtraction process, based on an output from the comparator, thereby decreasing the circuit scale and substantially eliminating occurrence of an error.

    摘要翻译： 为了解决由于使用DA转换器导致的电路规模增加和功耗增加的问题，半导体集成电路包括能够将增益切换为1或2的信号放大器2,10，运算处理器7 9，用于从输入信号执行参考电压的减法处理以输出其结果或用于在不执行减法处理的情况下输出输入信号;开关8，其一个开关端子连接到信号输入端子，其另一个开关 端子连接到采样保持电路5,6的输出侧，并且其公共端连接到算术处理器的输入侧;比较器3，用于将来自信号放大器的输出与参考电压进行比较，以二值化输出; 以及用于将信号放大器的输出侧连接到采样保持电路的输入侧的开关11，其中，算术处理器执行 基于比较器的输出，从输入信号执行参考电压的减法处理以输出结果和输出输入信号的操作而不执行减法处理的操作，从而减小电路规模并基本上消除发生 的错误。

    Semiconductor integrated circuit utilizing insulated gate type transistors
    52.
    发明授权
    Semiconductor integrated circuit utilizing insulated gate type transistors 失效
    采用绝缘栅型晶体管的半导体集成电路

    公开(公告)号：US6100741A

    公开(公告)日：2000-08-08

    申请号：US110012

    申请日：1998-07-02

    申请人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

    发明人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

    IPC分类号： G06G7/16 ,  G06G7/163 ,  G06F7/44

    CPC分类号： G06G7/163

    摘要： For raising the accuracy of analog multiplication, a gate-drain (G-D) connection point of transistor (Tr) whose gate-drain (G-D) are shorted and whose source is connected to ground potential is connected to a source of second Tr whose G-D are shorted, a first input signal current source is connected to a G-D connection point of the second Tr, a G-D connection point of third Tr whose G-D are shorted and whose source is connected to the ground potential is connected to a source of fourth Tr whose G-D are shorted, a second input signal current source is connected to a G-D connection point of the fourth Tr, the G-D connection points of the second and fourth Tr's are connected to first and second capacitors respectively, outputs of the first and second capacitors are connected to each other and to a gate of fifth Tr to form a floating point, a source of the fifth Tr is connected to the ground potential, and a drain current of the fifth Tr is an operation output.

    摘要翻译： 为了提高模拟倍增的精度，其栅极漏极（GD）短路并且其源极连接到地电位的晶体管（Tr）的栅极 - 漏极（GD）连接点连接到第二Tr的源极，其中GD为 短路时，第一输入信号电流源连接到第二Tr的GD连接点，GD短路的第三Tr的GD连接点和其源极连接到地电位，连接到第四Tr的源，其中GD 短路，第二输入信号电流源连接到第四Tr的GD连接点，第二和第四Tr的GD连接点分别连接到第一和第二电容器，第一和第二电容器的输出连接到 彼此并且连接到第五Tr的栅极以形成浮点，第五Tr的源极连接到地电位，并且第五Tr的漏极电流是操作输出。

    Semiconductor circuit capable of storing a plurality of analog or multi-valued data
    53.
    发明授权
    Semiconductor circuit capable of storing a plurality of analog or multi-valued data 失效
    能够存储多个模拟或多值数据的半导体电路

    公开(公告)号：US6011714A

    公开(公告)日：2000-01-04

    申请号：US19270

    申请日：1998-02-05

    申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Yuichiro Yamashita

    发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Yuichiro Yamashita

    IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C27/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C27/005 ,  G11C2211/5612

    摘要： A semiconductor circuit assembly is capable of accurately storing a plurality of analog or multi-valued data using circuitry having a small surface area. The circuit assembly includes a first circuit provided in the form of a target memory cell device comprising memory cells which conduct the writing and storage of analog signals. The first circuit has output terminals for outputting stored values to the exterior as voltage signals. Mechanisms supply at least two index voltages. A second circuit performs the function of halting the writing of the analog signals when the output signal at the first circuit output terminals reaches a value representing a desired voltage plus the difference between the two index voltages.

    摘要翻译： 半导体电路组件能够使用具有小表面积的电路来精确地存储多个模拟或多值数据。 电路组件包括以目标存储单元装置的形式提供的第一电路，其包括进行模拟信号的写入和存储的存储单元。 第一电路具有用于将存储的值作为电压信号输出到外部的输出端子。 机制提供至少两个指标电压。 当第一电路输出端的输出信号达到表示期望电压的值加上两个指标电压之间的差时，第二电路执行停止模拟信号写入的功能。

    Semiconductor arithmetic circuit
    55.
    发明授权
    Semiconductor arithmetic circuit 失效
    半导体运算电路

    公开(公告)号：US5923205A

    公开(公告)日：1999-07-13

    申请号：US930372

    申请日：1997-11-07

    申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Masahiro Konda

    发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Masahiro Konda

    IPC分类号： G06G7/26 ,  G06G7/42

    CPC分类号： G06G7/26

    摘要： A semiconductor arithemetic circuit which performs calculation of an analog vector with a high accuracy at a high speed. A semiconductor arithemetic circuit having a plurality of MOS type transistors, wherein the source electrodes are connected to one another, the gate electrodes of the MOS type transistors are connected to a signal line having a prescribed potential via switching elements, and at least one input electrode is capacitively coupled with the gate electrodes; wherein circuitry is provided for applying first and second input voltages, respectively, to the input electrodes of at least one pair of first and second MOS type transistors among the plurality of MOS type transistors, and for equalizing potentials of the gate electrodes to the potential of the signal line by allowing the switching elements to conduct, and further circuitry means is provided for inputting the second and first input voltages into, respectively, the input electrodes of the first and second MOS type transistors after placing said gate electrodes in an electrically floating state by turning the switching elements off.

    摘要翻译： PCT No.PCT / JP96 / 00882 Sec。 371日期：1997年11月7日 102（e）日期1997年11月7日PCT 1996年4月1日PCT PCT。 WO96 / 30853 PCT出版物 日期：1996年10月3日一种以高速度高精度地进行模拟矢量的计算的半导体仿真电路。 一种具有多个MOS型晶体管的半导体仿真电路，其中源极彼此连接，MOS型晶体管的栅电极通过开关元件连接到具有规定电位的信号线，并且至少一个输入电极 与栅电极电容耦合; 其中提供电路，用于将多个MOS型晶体管中的至少一对第一和第二MOS型晶体管的输入电极分别施加第一和第二输入电压，并将栅电极的电位与 信号线通过允许开关元件导通，并且还提供另外的电路装置，用于在将所述栅电极置于电浮动状态之后将第二和第一输入电压分别输入到第一和第二MOS型晶体管的输入电极中 通过关闭开关元件。

    Semiconductor circuit
    56.
    发明授权
    Semiconductor circuit 失效
    半导体电路

    公开(公告)号：US5784018A

    公开(公告)日：1998-07-21

    申请号：US702689

    申请日：1996-08-12

    申请人： Tadahiro Ohmi ,  Takeo Yamashita ,  Tadashi Shibata

    发明人： Tadahiro Ohmi ,  Takeo Yamashita ,  Tadashi Shibata

    IPC分类号： G11C11/56 ,  G11C27/00 ,  H03M1/12

    CPC分类号： G11C27/005 ,  G11C11/5621 ,  G11C11/54 ,  G11C2211/5611 ,  G11C7/16

    摘要： The invention provides a semiconductor circuit which can fetch and store analog and multilevel data by using a simple circuit. The invention also provides a multilevel memory which can freely change the number of quantizing levels by using external signals. This semiconductor circuit comprises a first circuit which converts first signals into a group of quantized signals, a second circuit which converts the signal group into second multilevel signals, and structure which feeds back the second signals to the first circuit as first signals. The semiconductor circuit further has a structure to electrically separates at least one signal included in the signal group from the input of the second circuit, and structure which feeds back the second signals to the input of the second circuit instead of the signal previously separated.

    摘要翻译： PCT No.PCT / JP95 / 00204 Sec。 371日期：1996年8月12日 102（e）日期1996年8月12日PCT提交1995年2月14日PCT公布。 WO95 / 22146 PCT公开号 日期：1995年8月17日本发明提供一种半导体电路，其可以通过使用简单的电路来获取和存储模拟和多电平数据。 本发明还提供一种可以通过使用外部信号自由地改变量化电平数量的多电平存储器。 该半导体电路包括将第一信号转换成一组量化信号的第一电路，将信号组转换成第二多电平信号的第二电路，以及将第二信号作为第一信号反馈到第一电路的结构。 半导体电路还具有将包括在信号组中的至少一个信号与第二电路的输入电隔离的结构，以及将第二信号反馈到第二电路的输入而不是先前分离的信号的结构。

    Semiconductor integrated circuit
    57.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US5682109A

    公开(公告)日：1997-10-28

    申请号：US600760

    申请日：1996-02-13

    申请人： Tadahiro Ohmi ,  Tadashi Shibata ,  Koji Kotani

    发明人： Tadahiro Ohmi ,  Tadashi Shibata ,  Koji Kotani

    IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/06 ,  G06N3/063 ,  G11C11/54 ,  H03K3/356 ,  H03K19/20 ,  G01R19/00

    CPC分类号： H03K3/356139 ,  H03K3/356104

    摘要： The present invention relates to a semiconductor integrated circuit. In greater detail, the present invention relates to a semiconductor integrated circuit which conducts calculations using a voltage adding function by means of capacity and threshold operations. The semiconductor integrated circuit in accordance with the present invention is characterized in that, in a circuit wherein the output of a first inverter circuit and the input of a second inverter circuit are connected at a first contact point, the output of the second inverter and the input of the first inverter are connected at a second contact point, and a means is provided for generating a difference in potential between the first contact point and the second contact point, an electrically floating electrode and a plurality of input electrodes, which are provided via capacity elements with this electrode, are provided, and a means is provided for in effect determining the difference in potential by means of the potentials applied to the input electrodes.

    摘要翻译： 半导体集成电路技术领域本发明涉及半导体集成电路。 更详细地说，本发明涉及利用容量和阈值操作使用加电功能进行计算的半导体集成电路。 根据本发明的半导体集成电路的特征在于，在第一反相器电路的输出和第二反相器电路的输入在第一接触点处连接的电路中，第二反相器的输出和 第一反相器的输入端连接在第二接触点处，并且提供用于产生第一接触点和第二接触点之间的电位差的装置，电浮动电极和多个输入电极，其经由 提供了具有该电极的电容元件，并且提供了用于通过施加到输入电极的电位实际上确定电位差的装置。

    Source follower using two pairs of NMOS and PMOS transistors
    58.
    发明授权
    Source follower using two pairs of NMOS and PMOS transistors 失效
    源极跟随器使用两对NMOS和PMOS晶体管

    公开(公告)号：US5469085A

    公开(公告)日：1995-11-21

    申请号：US87675

    申请日：1993-10-13

    申请人： Tadashi Shibata ,  Tadahiro Ohmi

    发明人： Tadashi Shibata ,  Tadahiro Ohmi

    IPC分类号： G06N3/063 ,  H01L27/115 ,  H01L29/788 ,  H03F3/50 ,  H03K17/00 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0948

    CPC分类号： G06N3/0635 ,  H01L27/115 ,  H01L29/7881 ,  H03F3/505 ,  H03K17/164 ,  H03K17/6872 ,  H03K2217/0036

    摘要： A source follower circuit which operates at high speed and maintains low power consumption and which includes a pair of small, normally on, NMOS and PMOS transistors and a pair of large, normally off, NMOS and PMOS transistors. The two pairs of transistors are connected in parallel. In each pair of transistors the sources and the gates of the NMOS and PMOS transistors are connected to each other. Furthermore, the threshold voltages of the transistors must be set so that: large NMOS transistor voltage>small PMOS transistor voltage>small NMOS transistor voltage>large PMOS transistor voltage, or so that small PMOS transistor voltage>large NMOS transistor voltage>large PMOS transistor voltage>small NMOS transistor voltage.

    摘要翻译： PCT No.PCT / JP92 / 00019 Sec。 371日期：1993年10月13日 102（e）日期1993年10月13日PCT提交1992年1月13日PCT公布。 出版物WO92 / 12575 日期1992年7月23日。源极跟随器电路以高速运行并保持低功耗，并且包括一对小的，常导通的NMOS和PMOS晶体管以及一对大的常闭NMOS和PMOS晶体管。 两对晶体管并联连接。 在每对晶体管中，NMOS和PMOS晶体管的源极和栅极彼此连接。 此外，晶体管的阈值电压必须设置为：大NMOS晶体管电压>小PMOS晶体管电压>小NMOS晶体管电压>大PMOS晶体管电压，或使PMOS晶体管电压小>大NMOS晶体管电压>大PMOS晶体管 电压>小型NMOS晶体管电压。

    DATA PROCESSING APPARATUS AND METHOD
    60.
    发明申请
    DATA PROCESSING APPARATUS AND METHOD 审中-公开
    数据处理装置和方法

    公开(公告)号：US20100182339A1

    公开(公告)日：2010-07-22

    申请号：US12668180

    申请日：2008-05-28

    申请人： Nobutaka Kitajima ,  Akira Tanaka ,  Tadashi Shibata

    发明人： Nobutaka Kitajima ,  Akira Tanaka ,  Tadashi Shibata

    IPC分类号： G09G5/00 ,  G06K9/36

    CPC分类号： H04N5/91 ,  G11B20/10527 ,  G11B27/3036 ,  G11B2020/10629 ,  G11B2020/10675 ,  G11B2020/10712 ,  G11B2020/10759 ,  G11B2220/2541 ,  H04N9/8042 ,  H04N9/8205 ,  H04N9/8227 ,  H04N19/44

    摘要： A stream processing section (12) analyzes input stream data and, if the stream data includes a compressed/coded graphics object, decodes the graphics object line by line and writes the decoded graphics object into a graphics object buffer (14), and, if the stream data includes control information of a graphics object, writes the control information into a control information buffer (13). A graphics control section (15) renders a graphics object stored in the graphics object buffer (14) in a graphics plane (16) based on control information stored in the control information buffer (13). When a decoding error has occurred, the stream processing section (12) restarts decoding from the next or a subsequent line.

    摘要翻译： 流处理部分（12）分析输入流数据，并且如果流数据包括压缩/编码图形对象，逐行解码图形对象，并将解码的图形对象写入图形对象缓冲器（14）中，并且如果 流数据包括图形对象的控制信息，将控制信息写入控制信息缓冲器（13）。 图形控制部分（15）基于存储在控制信息缓冲器（13）中的控制信息，在图形平面（16）中呈现存储在图形对象缓冲器（14）中的图形对象。 当发生解码错误时，流处理部分（12）从下一行或后续行重新开始解码。