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    Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop
    2.
    发明授权
    Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop 失效
    半导体集成电路，具有相同电路的延迟锁定环路，自同步管线型系统，压控振荡器和锁相环

    公开(公告)号：US06459312B2

    公开(公告)日：2002-10-01

    申请号：US09919926

    申请日：2001-08-02

    申请人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

    发明人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

    IPC分类号： H03L700

    CPC分类号： H03K3/0315 ,  H03K3/354 ,  H03K5/133 ,  H03K2005/00045 ,  H03L7/0812 ,  H03L7/0995 ,  H03L2207/06

    摘要： The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.

    摘要翻译： 通过其中信号输入端子通过第一电容器连接到读出放大器的输入端的电路来解决抖动量增加与延迟量增加的问题，控制输入端子通过第二电容器连接到输入端 读出放大器的端子和读出放大器的输入端与第一和第二电容器之间的公共连接点是浮动节点，并且其中通过信号输入端施加到读出放大器的输入端的信号是垂直的 至少在感测放大器的判定阈值附近，施加到控制输入端子的控制信号移位，从而控制输出的延迟量。

    Semiconductor integrated circuit for parallel signal processing
    3.
    发明授权
    Semiconductor integrated circuit for parallel signal processing 失效
    半导体集成电路并行信号处理

    公开(公告)号：US6127852A

    公开(公告)日：2000-10-03

    申请号：US110014

    申请日：1998-07-02

    申请人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

    发明人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

    IPC分类号： G01D1/12 ,  G06G7/12 ,  G06G7/122 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H03D1/00

    CPC分类号： G06G7/122

    摘要： To retrieve analog signals at high precision by a maximum or minimum position detection parallel signal processing circuit, a plurality of circuit units in each of which a gate of a transistor is connected to a signal input terminal through first capacitive means, a common connecting point of the gate and the first capacitive means is connected to one terminal side of second capacitive means, and control means, for fluctuating a voltage on the other terminal side of the second capacitive means so as to further increase or decrease a drain current in correspondence to an increase or decrease in the drain current is connected between the drain and the other terminal side of the second capacitive means are provided, a source of each transistor of the plurality of circuit units is commonly connected and is connected to a constant current source, and the maximum or minimum voltage position detection with respect to a signal voltage which is applied to each signal input terminal is performed by a voltage on the other terminal side of the second capacitive means.

    摘要翻译： 为了通过最大或最小位置检测并行信号处理电路以高精度检索模拟信号，通过第一电容装置将晶体管的栅极连接到信号输入端的多个电路单元中的多个电路单元， 栅极和第一电容装置连接到第二电容装置的一个端子侧，以及控制装置，用于使第二电容装置的另一个端子侧的电压波动，以进一步增加或减少对应于 在第二电容装置的漏极和另一个端子侧之间连接漏极电流的增加或减少，多个电路单元中的每个晶体管的源极共同连接并连接到恒定电流源，并且 执行相对于施加到每个信号输入端子的信号电压的最大或最小电压位置检测 通过第二电容装置的另一个端子侧的电压。

    Semiconductor arithmetic apparatus
    4.
    发明授权
    Semiconductor arithmetic apparatus 失效
    半导体运算装置

    公开(公告)号：US6115725A

    公开(公告)日：2000-09-05

    申请号：US14644

    申请日：1998-01-28

    申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Akira Nataka ,  Tatsuo Morimoto ,  Masahiro Konda

    发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Akira Nataka ,  Tatsuo Morimoto ,  Masahiro Konda

    IPC分类号： G06T9/00 ,  H03M7/30 ,  G06F7/00 ,  H04N7/12

    CPC分类号： H03M7/3082 ,  G06T9/008 ,  H04N19/94

    摘要： The real time compression of moving images employing vector quantization is realized using simple hardware and with an optimal compression ratio with respect to the communication line capacity employed. In the operating system, which is provided with a first mechanism (202), comprising a plurality of groups of numerical values, a second mechanism (201), a first circuit (206), a second circuit (206), and a third circuit (210), the second circuit comprises a plurality of fourth circuits divided into two or more groups (210-213, 219, and 301), the fourth circuits have a plurality of input terminals and at least one output terminal, and a mechanism is provided having a structure wherein various signals expressing degrees of similarity are inputted into the plurality of input terminals, only that signal having the largest degree of similarity among the variety of signals expressing degrees of similarity which are inputted is outputted from the output terminal, and the output signal of a predetermined first group among the two or more groups is inputted into an input terminal of a second group, whereby only one first vector having the largest degree of similarity is selected.

    摘要翻译： 使用矢量量化的运动图像的实时压缩是使用简单的硬件和相对于所采用的通信线路容量的最佳压缩比来实现的。 在具有第一机构（202）的操作系统中，包括多组数值，第二机构（201），第一电路（206），第二电路（206）和第三电路 （210），所述第二电路包括分成两组或更多组（210-213,219和301）的多个第四电路，所述第四电路具有多个输入端子和至少一个输出端子，并且机构是 具有这样的结构，其中表示相似度的各种信号被输入到多个输入端，只有表示输入的相似度的各种信号之间具有最大相似程度的信号从输出端输出， 将两个以上组中的预定第一组的输出信号输入到第二组的输入端，由此仅选择具有最大相似度的一个第一矢量。

    Semiconductor circuitry to process analog signals using weighted- sum operations
    5.
    发明授权
    Semiconductor circuitry to process analog signals using weighted- sum operations 失效
    半导体电路，用加权和运算处理模拟信号

    公开(公告)号：US5939925A

    公开(公告)日：1999-08-17

    申请号：US930508

    申请日：1997-11-07

    申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Ning Mei Yu ,  Tsutomu Nakai

    发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Ning Mei Yu ,  Tsutomu Nakai

    IPC分类号： G06F17/16 ,  G06J1/00 ,  G06K9/64 ,  G06G7/12

    CPC分类号： G06K9/64 ,  G06F17/16 ,  G06J1/00

    摘要： A semiconductor operational circuit conducts real-time analog vector operations to permit the determination of the center of gravity of an image of a moving object. The circuit employs a first processing stage utilizing CMOS source follower circuits to perform weighted linear sum operations on the analog signals. A second processing stage utilizes comparator circuitry to perform comparison operations involving data from the weighted-sum and non-weighted-sum operations. A third processing stage utilizes exclusive OR gates to provide digital data outputs based on the comparison operation results.

    摘要翻译： PCT No.PCT / JP96 / 00883 Sec。 371日期：1997年11月7日 102（e）日期1997年11月7日PCT 1996年4月1日PCT PCT。 出版物WO96 / 30827 日期1996年10月3日半导体运算电路进行实时模拟矢量运算，以确定移动物体的图像的重心。 电路采用利用CMOS源极跟随器电路的第一处理级，对模拟信号执行加权线性和运算。 第二处理阶段利用比较器电路执行涉及来自加权和和非加权和运算的数据的比较运算。 第三处理级利用异或门来提供基于比较运算结果的数字数据输出。

    Method of forming a monocrystalline film having a closed loop step portion on the substrate
    7.
    发明授权
    Method of forming a monocrystalline film having a closed loop step portion on the substrate 失效
    在基板上形成具有闭环台阶部分的单晶膜的方法

    公开(公告)号：US5362672A

    公开(公告)日：1994-11-08

    申请号：US465175

    申请日：1990-02-01

    申请人： Tadahiro Ohmi ,  Tadashi Shibata ,  Masaru Umeda

    发明人： Tadahiro Ohmi ,  Tadashi Shibata ,  Masaru Umeda

    IPC分类号： C23C14/06 ,  H01L21/20 ,  H01L21/203 ,  H01L21/336 ,  H01L21/84

    CPC分类号： H01L29/66772 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02491 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/84 ,  Y10S148/158

    摘要： A method of manufacturing a semiconductor device, and particularly a method of forming a monocrystalline film on a substrate. The method includes the step of forming a conductor layer having a step portion on the surface of a substrate. The step portion includes a lateral face which surrounds the lower surface of the step portion to form a closed loop. After the conductor layer has been formed on the surface of the substrate, a monocrystalline film is formed directly on the substrate. Specifically, the film is formed on the lower surface of the step portion, while a DC potential is applied to the conductor layer.

    摘要翻译： PCT No.PCT / JP89 / 00599 Sec。 371日期1990年2月1日 102（e）1990年2月1日PCT PCT。1989年6月15日PCT公布。 公开号WO89 / 12908 日期：1989年12月28日。一种制造半导体器件的方法，特别是在衬底上形成单晶膜的方法。 该方法包括在衬底的表面上形成具有台阶部分的导体层的步骤。 台阶部分包括侧面，该侧面围绕台阶部分的下表面以形成闭环。 在衬底表面上形成导体层之后，直接在衬底上形成单晶膜。 具体地，在台阶部的下表面上形成膜，同时对导体层施加DC电位。

    Neuron circuit
    8.
    发明授权
    Neuron circuit 失效
    神经元电路

    公开(公告)号：US5258657A

    公开(公告)日：1993-11-02

    申请号：US777352

    申请日：1992-01-06

    申请人： Tadashi Shibata ,  Tadahiro Ohmi

    发明人： Tadashi Shibata ,  Tadahiro Ohmi

    IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/063 ,  G06N99/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H03K19/08 ,  H03K19/23

    CPC分类号： G06N3/0635 ,  H01L27/115 ,  H01L29/7881 ,  H01L2924/0002

    摘要： A semiconductor device of this invention comprises on a substrate a first semiconductor region of one conductive type, first source and drain regions of the opposite conductive type formed in said semiconductor region, a first gate electrode formed in a region separating said source and drain regions, the first gate electrode being electrically floating through an insulating film, and at least two second gate electrodes connected to said first gate electrode by capacitive coupling, wherein an inversion layer is formed under said first gate electrode and said first source and drain regions are electrically connected together only when a predetermined threshold value is exceeded by the absolute value of a value obtained by linearly summing up the weighted voltages applied to said second gate electrodes.

    Semiconductor arithmetic unit
    10.
    发明授权
    Semiconductor arithmetic unit 失效
    半导体运算单元

    公开(公告)号：US06704757B1

    公开(公告)日：2004-03-09

    申请号：US09673516

    申请日：2001-01-02

    申请人： Tadahiro Ohmi ,  Tadashi Shibata ,  Akira Nakada ,  Tatsuro Morimoto ,  Takahisa Nitta

    发明人： Tadahiro Ohmi ,  Tadashi Shibata ,  Akira Nakada ,  Tatsuro Morimoto ,  Takahisa Nitta

    IPC分类号： G06J100

    CPC分类号： G06N3/063 ,  G06N3/0635

    摘要： A semiconductor arithmetic unit which realizes a maximum or minimum value retrieval operation at high speed and with a high degree of accuracy used in a vector quantization processor is composed of a binary-multivalue-analog merged operation processing circuit. A multi-loop circuit includes an amplifying circuit group composed of a plurality of sets of first amplifiers with a floating gate to which first electrodes and a single second electrode are capacitively coupled with a predetermined ratio, a logical operation circuit to which output signals of the amplifying circuit group are inputted and which outputs a logical 0 or 1, and a second amplifying circuit to which an output signal of the logical operation circuit is inputted and whose output is distributed to all of the second electrodes of the amplifying circuit group. The second amplifying circuit includes an adjusting circuit which adjusts an output current driving ability and a controlling circuit which controls the adjustment with a predetermined regulation. The adjustment of the controlling circuit is executed according to variation of the output of the logical operation circuit.

    摘要翻译： 实现在矢量量化处理器中使用的高速度和高精度的最大值或最小值检索操作的半导体运算单元由二进制多值模拟合并运算处理电路构成。 多回路电路包括由具有浮置栅极的多组第一放大器组成的放大电路组，第一电极和单个第二电极以预定比率电容耦合到该第一放大器;逻辑运算电路， 输入逻辑0或1的放大电路组，输入逻辑运算电路的输出信号并将其输出分配给放大电路组的所有第二电极的第二放大电路。 第二放大电路包括调节输出电流驱动能力的调节电路和控制电路，控制电路以预定的调节进行调节。 控制电路的调整根据逻辑运算电路的输出的变化进行。