公开(公告)号：US09859156B2

公开(公告)日：2018-01-02

申请号：US14985157

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01L21/7685 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295

Abstract: An interconnection structure includes a non-insulator structure, a dielectric structure, a conductive structure and a first dielectric protective layer. The dielectric structure is present on the non-insulator structure. The dielectric structure has a trench opening and a via opening therein. The via opening is present between the trench opening and the non-insulator structure. The conductive structure is present in the trench opening and the via opening and electrically connected to the non-insulator structure. The first dielectric protective layer is present between the conductive structure and at least one sidewall of the trench opening.

公开(公告)号：US09847330B2

公开(公告)日：2017-12-19

申请号：US15071207

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: Fin field effect transistors (FinFETs) and method for fabricating the same are disclosed. One of the FinFETs includes a substrate, an insulator, first and second gates, an opening, first and second dielectric layers. The substrate includes first and second semiconductor fins and a trench therebetween. The insulator is disposed in the trench. The first and second gates are respectively disposed on the first and second semiconductor fins. The opening is disposed between the first gate and the second gate. The first dielectric layer is disposed in the opening to electrically insulate the first and second gates and includes a slit. The second dielectric layer is filled in the slit, wherein the opening has a first width in a direction along which the first and second gates extend, the slit has a second width in the direction, and a ratio of the first width to the second width is larger than 2.

公开(公告)号：US09793407B2

公开(公告)日：2017-10-17

申请号：US14968906

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/785

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

公开(公告)号：US09786505B2

公开(公告)日：2017-10-10

申请号：US14984555

申请日：2015-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/06 ,  H01L21/225 ,  H01L29/66

CPC classification number: H01L21/2253 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate, at least one active semiconductor fin, at least one insulating structure, a gate electrode, and a gate dielectric. The active semiconductor fin is disposed on the substrate. The insulating structure is disposed on the substrate and adjacent to the active semiconductor fin. A top surface of the insulating structure is non-concave and is lower than a top surface of the active semiconductor fin. The gate electrode is disposed over the active semiconductor fin. The gate dielectric is disposed between the gate electrode and the active semiconductor fin.

公开(公告)号：US09773871B2

公开(公告)日：2017-09-26

申请号：US14941664

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L29/1083 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET includes a substrate, a plurality of insulators disposed on the substrate, a gate stack and a strained material. The substrate includes at least one semiconductor fin and the semiconductor fin includes at least one modulation portion distributed therein. The semiconductor fin is sandwiched by the insulators. The gate stack is disposed over portions of the semiconductor fin and over portions of the insulators. The strained material covers portions of the semiconductor fin that are revealed by the gate stack. In addition, a method for fabricating the FinFET is provided.

公开(公告)号：US20170229451A1

公开(公告)日：2017-08-10

申请号：US15071207

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: Fin field effect transistors (FinFETs) and method for fabricating the same are disclosed. One of the FinFETs includes a substrate, an insulator, first and second gates, an opening, first and second dielectric layers. The substrate includes first and second semiconductor fins and a trench therebetween. The insulator is disposed in the trench. The first and second gates are respectively disposed on the first and second semiconductor fins. The opening is disposed between the first gate and the second gate. The first dielectric layer is disposed in the opening to electrically insulate the first and second gates and includes a slit. The second dielectric layer is filled in the slit, wherein the opening has a first width in a direction along which the first and second gates extend, the slit has a second width in the direction, and a ratio of the first width to the second width is larger than 2.

公开(公告)号：US20170194458A1

公开(公告)日：2017-07-06

申请号：US14985406

申请日：2015-12-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/30 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/30 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/7856

Abstract: a semiconductor device including a substrate, a plurality of insulators, a dielectric layer and a plurality of gates is provided. The substrate includes a plurality of trenches and a semiconductor fin between trenches. The insulators are disposed in the trenches. The dielectric layer covers the semiconductor fin and the insulators. A lengthwise direction of the gates is different from a lengthwise direction of the semiconductor fin. The gates comprise at least one first gate that is penetrated by the semiconductor fin and at least one second gate that is not penetrated through by the semiconductor fin. The second gate comprises a broadened portion disposed on the dielectric layer and a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.

公开(公告)号：US20170170322A1

公开(公告)日：2017-06-15

申请号：US14968910

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02631 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/76841 ,  H01L21/76879 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin-type field effect transistor device including a substrate, at least one gate stack structure, spacers and source and drain regions is described. The gate stack structure is disposed on the substrate and the spacers are disposed on sidewalls of the gate stack structure. The source and drain regions are disposed in the substrate and located at opposite sides of the gate stack structures. A dielectric layer having contact openings is disposed over the substrate and covers the gate stack structures. Metal connectors are disposed within the contact openings and connected to the source and drain regions, and adhesion layers are sandwiched between the contact openings and the metal connectors located within the contact openings.

公开(公告)号：US20170141106A1

公开(公告)日：2017-05-18

申请号：US14941673

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

公开(公告)号：US20170140992A1

公开(公告)日：2017-05-18

申请号：US14941679

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/76224 ,  H01L21/823418 ,  H01L27/0886 ,  H01L29/06 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/201 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: A FinFET including a substrate, a plurality of insulators disposed on the substrate, a gate stack and a strained material is provided. The substrate includes a plurality of semiconductor fins. The semiconductor fins include at least one active fin and a plurality of dummy fins disposed at two opposite sides of the active fin. The insulators are disposed on the substrate and the semiconductor fins are insulated by the insulators. The gate stack is disposed over portions of the semiconductor fins and over portions of the insulators. The strained material covers portions of the active fin that are revealed by the gate stack. In addition, a method for fabricating the FinFET is provided.