公开(公告)号：US09607838B1

公开(公告)日：2017-03-28

申请号：US14859165

申请日：2015-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chang Lin ,  Chun-Feng Nieh ,  Huicheng Chang ,  Hou-Yu Chen ,  Yong-Yan Lu

IPC: H01L21/8238 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7855

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

公开(公告)号：US09412836B2

公开(公告)日：2016-08-09

申请号：US14198841

申请日：2014-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Ting Wang ,  Teng-Chun Tsai ,  Cheng-Tung Lin ,  Hung-Ta Lin ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/36 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66522 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/365 ,  H01L29/78

Abstract: The present disclosure relates to a semiconductor device having a delta doped sheet layer within a transistor's source/drain region to reduce contact resistance, and an associated method. In some embodiments, a dielectric layer is disposed over the transistor. A trench is disposed through the dielectric layer to the source/drain region and a conductive contact is disposed in the trench. The source/drain region comprises a delta doped sheet layer with a doping concentration that is higher than rest of the source/drain region.

Abstract translation: 本发明涉及一种半导体器件，其具有在晶体管的源极/漏极区域内的δ掺杂片层，以降低接触电阻，以及相关联的方法。 在一些实施例中，介电层设置在晶体管的上方。 沟槽通过电介质层设置到源极/漏极区域，并且导电接触件设置在沟槽中。 源极/漏极区域包括掺杂浓度高于源极/漏极区域的掺杂浓度的δ掺杂片层。

公开(公告)号：US12266574B2

公开(公告)日：2025-04-01

申请号：US17738527

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Teng ,  Chen-Fong Tsai ,  Li-Chi Yu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/3105 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78

Abstract: FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.

公开(公告)号：US12199156B2

公开(公告)日：2025-01-14

申请号：US17650329

申请日：2022-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Yi-Syuan Siao ,  Su-Hao Liu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.

公开(公告)号：US20240379461A1

公开(公告)日：2024-11-14

申请号：US18784355

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/762 ,  H01L27/092

Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

公开(公告)号：US20240379446A1

公开(公告)日：2024-11-14

申请号：US18782255

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Tien-Shun Chang ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/223 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.

公开(公告)号：US12087847B2

公开(公告)日：2024-09-10

申请号：US17809976

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chien-Tai Chan ,  Liang-Yin Chen ,  Yee-Chia Yeo ,  Szu-Ying Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L21/823431 ,  H01L29/785

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

公开(公告)号：US12074068B2

公开(公告)日：2024-08-27

申请号：US17461271

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith Khaderbad ,  Sathaiya Mahaveer Dhanyakumar ,  Huicheng Chang ,  Keng-Chu Lin ,  Winnie Victoria Wei-Ning Chen

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L21/8221 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/092

Abstract: A semiconductor device includes a first transistor device of a first type. The first transistor includes first nanostructures, a first pair of source/drain structures, and a first gate electrode on the first nanostructures. The semiconductor device also includes a second transistor device of a second type formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate electrode on the second nanostructures and over the first nanostructures. The semiconductor device also includes a first isolation structure between the first and second nanostructures. The semiconductor device further includes a second isolation structure in contact with a top surface of the first pair of source/drain structures. The semiconductor device also includes a seed layer between the second isolation structure and the second pair of source/drain structures.

公开(公告)号：US12040382B2

公开(公告)日：2024-07-16

申请号：US17322405

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chi Yu ,  Cheng-I Chu ,  Chen-Fong Tsai ,  Yi-Rui Chen ,  Sen-Hong Syue ,  Wen-Kai Lin ,  Yoh-Rong Liu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/02236 ,  H01L21/0259 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

公开(公告)号：US20240203749A1

公开(公告)日：2024-06-20

申请号：US18415411

申请日：2024-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chia-Cheng Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/32 ,  G03F7/00 ,  H01L21/027

CPC classification number: H01L21/32 ,  G03F7/70283 ,  H01L21/027

Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.