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    SEMICONDUCTOR DEVICE STRUCTURE WITH A CONDUCTIVE FEATURE PASSING THROUGH A PASSIVATION LAYER
    51.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE WITH A CONDUCTIVE FEATURE PASSING THROUGH A PASSIVATION LAYER 审中-公开

    公开(公告)号：US20200258931A1

    公开(公告)日：2020-08-13

    申请号：US16861453

    申请日：2020-04-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsun-Ying Huang

    IPC: H01L27/146 ,  H01L23/48

    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.

    MULTIPLE DEEP TRENCH ISOLATION (MDTI) STRUCTURE FOR CMOS IMAGE SENSOR
    53.
    发明申请
    MULTIPLE DEEP TRENCH ISOLATION (MDTI) STRUCTURE FOR CMOS IMAGE SENSOR 审中-公开

    公开(公告)号：US20200058685A1

    公开(公告)日：2020-02-20

    申请号：US16661136

    申请日：2019-10-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei Chuang Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Jen-Cheng Liu ,  Yen-Ting Chiang ,  Chun-Yuan Chen ,  Shen-Hui Hong

    IPC: H01L27/146 ,  H04N5/374 ,  H04N5/369

    Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. The photodiode comprises a doped layer with a first doping type and an adjoining region of the substrate with a second doping type that is different than the first doping type. A boundary deep trench isolation (BDTI) structure is disposed between adjacent pixel regions. A multiple deep trench isolation (MDTI) structure overlies the doped layer of the photodiode. The MDTI structure comprises a stack of dielectric layers lining sidewalls of a MDTI trench. A plurality of color filters is disposed at the back-side of the substrate corresponding to the respective photodiode of the plurality of pixel regions and overlying the MDTI structure.

    Back-side deep trench isolation (BDTI) structure for pinned photodiode image sensor
    57.
    发明授权
    Back-side deep trench isolation (BDTI) structure for pinned photodiode image sensor 有权

    公开(公告)号：US10304886B2

    公开(公告)日：2019-05-28

    申请号：US15795681

    申请日：2017-10-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Ting Chiang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jen-Cheng Liu ,  Yu-Jen Wang ,  Chun-Yuan Chen

    IPC: H01L27/146

    Abstract: The present disclosure relates to a CMOS image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. A back-side deep trench isolation (BDTI) structure is disposed between adjacent pixel regions, extending from a back-side of the substrate to a position within the substrate. The BDTI structure comprises a doped layer lining a sidewall surface of a deep trench and a dielectric fill layer filling a remaining space of the deep trench. By forming the disclosed BDTI structure that functions as a doped well and an isolation structure, the implantation processes from a front-side of the substrate is simplified, and thus the exposure resolution, the full well capacity of the photodiode, and the pinned voltage is improved.

    SEMICONDUCTOR DEVICE STRUCTURE WITH STACKED SEMICONDUCTOR DIES
    60.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE WITH STACKED SEMICONDUCTOR DIES 审中-公开

    公开(公告)号：US20180204868A1

    公开(公告)日：2018-07-19

    申请号：US15921032

    申请日：2018-03-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsun-Ying Huang

    IPC: H01L27/146 ,  H01L23/48

    CPC classification number: H01L27/14634 ,  H01L23/481 ,  H01L27/14636 ,  H01L2224/11

    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.

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