公开(公告)号：US20190244834A1

公开(公告)日：2019-08-08

申请号：US16389993

申请日：2019-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chung-Hao Tsai ,  Chun-Lin Lu ,  Yen-Ping Wang ,  Che-Wei Hsu

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L21/768 ,  H01L23/31

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The first redistribution structure has a dielectric layer and a feed line disposed on the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The insulation encapsulation has a protrusion laterally wraps around the feed line. The insulation encapsulation has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The second redistribution structure is disposed on the die and the insulation encapsulation.

公开(公告)号：US20190139897A1

公开(公告)日：2019-05-09

申请号：US15841331

申请日：2017-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang-Yu Liang ,  Kai-Chiang Wu

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01Q1/22

Abstract: A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.

公开(公告)号：US20190123017A1

公开(公告)日：2019-04-25

申请号：US16223274

申请日：2018-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Chia-Chun Miao ,  Hung-Jen Lin

IPC: H01L23/00

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

公开(公告)号：US20190067039A1

公开(公告)日：2019-02-28

申请号：US15690300

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chung-Hao Tsai ,  Chun-Lin Lu ,  Yen-Ping Wang ,  Che-Wei Hsu

IPC: H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The second redistribution structure is disposed on the die and the insulation encapsulation. At least one of the first redistribution structure and the second redistribution structure includes a dielectric layer, a feed line, and a signal enhancement layer. The feed line is at least partially disposed on the dielectric layer. The signal enhancement layer covers the feed line. The signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer.

公开(公告)号：US10163854B2

公开(公告)日：2018-12-25

申请号：US15803673

申请日：2017-11-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chuei-Tang Wang ,  Kai-Chiang Wu ,  Chieh-Yen Chen ,  Yen-Ping Wang ,  Shou-Zen Chang

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/03 ,  H01L23/31

Abstract: A package structure includes a package, at least one second molding material, and at least one electronic component. The package includes at least one first semiconductor device therein, a first molding material, at least one dielectric layer and at least one redistribution line. The first molding material is at least in contact with at least one sidewall of the first semiconductor device. The dielectric layer is over the first semiconductor device and the first molding material. The redistribution line is present at least partially in the dielectric layer and is electrically connected to the first semiconductor device. The second molding material is present on the package. The electronic component is present on the package and is external to the second molding material.

公开(公告)号：US20230369259A1

公开(公告)日：2023-11-16

申请号：US18358991

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kai-Chiang Wu ,  Chung-Shi Liu ,  Shou Zen Chang ,  Chao-Wen Shih

IPC: H01L23/66 ,  H01L23/538 ,  H01P3/00 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01Q9/04 ,  H01Q1/38 ,  H01L21/78 ,  H01L23/552 ,  H01L25/00 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/06

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01P3/003 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q9/0457 ,  H01L21/486 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/214 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/3025 ,  H01Q21/065

Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.

公开(公告)号：US11309242B2

公开(公告)日：2022-04-19

申请号：US16915964

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang-Yu Liang ,  Kai-Chiang Wu

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31

Abstract: A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes an insulating layer, a functional circuit structure embedded in the insulating layer within a functional circuit region, and a seal ring structure embedded in the insulating layer within the seal ring region surrounding the functional circuit region. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure. The seal ring structure includes a stack of alternating interconnect layers and via patterns, and the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the seal ring region.

公开(公告)号：US20220013463A1

公开(公告)日：2022-01-13

申请号：US16924130

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chin-Liang Chen ,  Jiun-Yi Wu ,  Yen-Ping Wang

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.

公开(公告)号：US20210407904A1

公开(公告)日：2021-12-30

申请号：US16915964

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang-Yu Liang ,  Kai-Chiang Wu

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/528

Abstract: A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes an insulating layer, a functional circuit structure embedded in the insulating layer within a functional circuit region, and a seal ring structure embedded in the insulating layer within the seal ring region surrounding the functional circuit region. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure. The seal ring structure includes a stack of alternating interconnect layers and via patterns, and the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the seal ring region.

公开(公告)号：US20210375809A1

公开(公告)日：2021-12-02

申请号：US16885297

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang-Yu Liang ,  Hsiu-Jen Lin ,  Kai-Chiang Wu ,  Chih-Chiang Tsao

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die laterally covered by an insulating encapsulation, a first redistribution structure disposed on the semiconductor die and the insulating encapsulation, a second redistribution structure disposed opposite to the first redistribution structure, and a through insulating via (TIV) penetrating through the insulating encapsulation. The semiconductor die is electrically coupled to the first redistribution structure through the second redistribution structure and the TIV. The first redistribution structure includes a patterned conductive layer covered by a patterned dielectric layer, and under-ball metallurgy (UBM) pattern partially covered by the patterned dielectric layer. A first portion of the UBM pattern physically contacts a via portion of the patterned conductive layer which is tapered toward the UBM pattern, and a second portion of the UBM pattern is connected to the first portion and protruded from the patterned dielectric layer.