公开(公告)号：US20190139897A1

公开(公告)日：2019-05-09

申请号：US15841331

申请日：2017-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang-Yu Liang ,  Kai-Chiang Wu

IPC分类号： H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01Q1/22

摘要： A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.

公开(公告)号：US20190123017A1

公开(公告)日：2019-04-25

申请号：US16223274

申请日：2018-12-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Lin Lu ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Chia-Chun Miao ,  Hung-Jen Lin

IPC分类号： H01L23/00

摘要： Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

公开(公告)号：US20190067039A1

公开(公告)日：2019-02-28

申请号：US15690300

申请日：2017-08-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Chiang Wu ,  Chung-Hao Tsai ,  Chun-Lin Lu ,  Yen-Ping Wang ,  Che-Wei Hsu

IPC分类号： H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78

摘要： An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The second redistribution structure is disposed on the die and the insulation encapsulation. At least one of the first redistribution structure and the second redistribution structure includes a dielectric layer, a feed line, and a signal enhancement layer. The feed line is at least partially disposed on the dielectric layer. The signal enhancement layer covers the feed line. The signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer.

公开(公告)号：US10163854B2

公开(公告)日：2018-12-25

申请号：US15803673

申请日：2017-11-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chuei-Tang Wang ,  Kai-Chiang Wu ,  Chieh-Yen Chen ,  Yen-Ping Wang ,  Shou-Zen Chang

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/03 ,  H01L23/31

摘要： A package structure includes a package, at least one second molding material, and at least one electronic component. The package includes at least one first semiconductor device therein, a first molding material, at least one dielectric layer and at least one redistribution line. The first molding material is at least in contact with at least one sidewall of the first semiconductor device. The dielectric layer is over the first semiconductor device and the first molding material. The redistribution line is present at least partially in the dielectric layer and is electrically connected to the first semiconductor device. The second molding material is present on the package. The electronic component is present on the package and is external to the second molding material.

公开(公告)号：US20240297131A1

公开(公告)日：2024-09-05

申请号：US18663697

申请日：2024-05-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Hao Tsai ,  Chia-Chia Lin ,  Kai-Chiang Wu ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/525 ,  H01L23/66 ,  H01L25/065 ,  H01L25/07

CPC分类号： H01L24/04 ,  H01L21/486 ,  H01L21/56 ,  H01L23/145 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/66 ,  H01L24/13 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/071 ,  H01L28/10 ,  H01L21/561 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/10122 ,  H01L2224/13024 ,  H01L2224/18 ,  H01L2224/92244

摘要： An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

公开(公告)号：US11515274B2

公开(公告)日：2022-11-29

申请号：US16885297

申请日：2020-05-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang-Yu Liang ,  Hsiu-Jen Lin ,  Kai-Chiang Wu ,  Chih-Chiang Tsao

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/498

摘要： A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die laterally covered by an insulating encapsulation, a first redistribution structure disposed on the semiconductor die and the insulating encapsulation, a second redistribution structure disposed opposite to the first redistribution structure, and a through insulating via (TIV) penetrating through the insulating encapsulation. The semiconductor die is electrically coupled to the first redistribution structure through the second redistribution structure and the TIV. The first redistribution structure includes a patterned conductive layer covered by a patterned dielectric layer, and under-ball metallurgy (UBM) pattern partially covered by the patterned dielectric layer. A first portion of the UBM pattern physically contacts a via portion of the patterned conductive layer which is tapered toward the UBM pattern, and a second portion of the UBM pattern is connected to the first portion and protruded from the patterned dielectric layer.

公开(公告)号：US11417616B2

公开(公告)日：2022-08-16

申请号：US16924116

申请日：2020-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Chiang Wu ,  Han-Ping Pu ,  Yen-Ping Wang

IPC分类号： H01L23/66 ,  H01L23/498 ,  H01L23/544 ,  H01L21/56 ,  H01L23/31

摘要： A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.

公开(公告)号：US11373922B2

公开(公告)日：2022-06-28

申请号：US16993285

申请日：2020-08-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sen-Kuei Hsu ,  Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Yi-Che Chiang

IPC分类号： H01L23/52 ,  H01L23/367 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/538

摘要： A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.

公开(公告)号：US11348874B2

公开(公告)日：2022-05-31

申请号：US16924130

申请日：2020-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Chiang Wu ,  Chin-Liang Chen ,  Jiun-Yi Wu ,  Yen-Ping Wang

IPC分类号： H01L23/538 ,  H01L25/00 ,  H01L23/31 ,  H01L25/065

摘要： A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.

公开(公告)号：US11264316B2

公开(公告)日：2022-03-01

申请号：US16513730

申请日：2019-07-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chuei-Tang Wang ,  Chun-Lin Lu ,  Kai-Chiang Wu

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/66 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L23/31 ,  H01Q1/22 ,  H01Q9/16 ,  H01Q9/04

摘要： A package structure includes a first RDL structure, a die, an encapsulant, a film, a TIV and a second RDL structure. The die is located over the first RDL structure. The encapsulant laterally encapsulates sidewalls of the die. The film is disposed between the die and the first RDL structure, and between the encapsulant and the first RDL structure. The TIV penetrates through the encapsulant and the film to connect to the first RDL structure. The second RDL structure is disposed on the die, the TIV and the encapsulant and electrically connected to die and the TIV.