公开(公告)号：US11450660B2

公开(公告)日：2022-09-20

申请号：US16859992

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-An Chen

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a gate dielectric layer, a high-k dielectric layer, and a protection cap. The substrate includes a first region, a second region, and a transition region located between the first region and the second region. The isolation structure, located in the transition region. The gate dielectric layer is located on the isolation structure. The high-k dielectric layer is located on the isolation structure and extended to cover a sidewall and a surface of the gate dielectric layer. The protection cap is located on a surface and sidewalls of the high-k dielectric layer.

公开(公告)号：US11355507B2

公开(公告)日：2022-06-07

申请号：US16887749

申请日：2020-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Te-An Chen

IPC: H01L27/11556 ,  H01L21/033 ,  H01L29/06 ,  H01L27/11582

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US20220037362A1

公开(公告)日：2022-02-03

申请号：US17140888

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/1159

Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

公开(公告)号：US20220036931A1

公开(公告)日：2022-02-03

申请号：US17081380

申请日：2020-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: G11C8/14 ,  H01L27/11597 ,  H01L27/105 ,  H01L21/822 ,  H01L21/8239

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length second edge of the memory array; a memory film contacting a first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

公开(公告)号：US20220020770A1

公开(公告)日：2022-01-20

申请号：US17018114

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L29/66 ,  H01L29/78 ,  G11C11/22 ,  G11C5/06

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

公开(公告)号：US11211388B2

公开(公告)日：2021-12-28

申请号：US16022702

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei-Cheng Wu ,  Li-Feng Teng ,  Chien-Hung Chang

IPC: H01L27/112 ,  H01L29/06 ,  H01L23/00 ,  H01L21/765 ,  H01L29/40 ,  H01L29/66 ,  H01L27/11534 ,  H01L21/762 ,  H01L27/11524 ,  H01L27/11546 ,  H01L21/28

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

公开(公告)号：US11211297B2

公开(公告)日：2021-12-28

申请号：US16984133

申请日：2020-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chia-Lin Liang ,  Chih-Ren Hsieh

IPC: G01R31/28 ,  H01L21/66 ,  H01L27/11517 ,  H01L21/28 ,  H01L29/423

Abstract: Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region. Second conductive layer formed extending in first direction over first conductive layer. Second conductive layer is patterned to form opening extending in first direction in central region of second conductive layer exposing portion of first conductive layer. First conductive layer exposed portion is removed exposing portion of diffusion region. Source/drain region is formed over exposed portion of diffusion region, and dielectric layer is formed over source/drain region. Third conductive layer is formed over dielectric layer. End portions along first direction of second conductive layer removed to expose first and second end portions of first conductive layer. Electrical resistance across first conductive layer between first and second end portions of first conductive layer is measured.

公开(公告)号：US20210391331A1

公开(公告)日：2021-12-16

申请号：US16901885

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L27/108 ,  H01L29/423 ,  H01L49/02

Abstract: An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

公开(公告)号：US20210375919A1

公开(公告)日：2021-12-02

申请号：US17122228

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chen Wang ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/522

Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

公开(公告)号：US20210343704A1

公开(公告)日：2021-11-04

申请号：US16861215

申请日：2020-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-An Chen

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/417

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first gate structure disposed on the substrate within the first region, a first S/D region, a first S/D contact, a second gate structure on the substrate within the second region, a second S/D region and a second S/D contact. The first S/D region is disposed in the substrate within the first region and beside the first gate structure. The first S/D contact is connected to the first S/D region. The second S/D region is disposed in the substrate within the second region and beside the second gate structure. The second S/D contact is connected to the second S/D region. The contact area between the second S/D region and the second S/D contact is larger than a contact area between the first S/D region and the first S/D contact.