公开(公告)号：US20230387263A1

公开(公告)日：2023-11-30

申请号：US18361540

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chun-Hsiang Fan ,  Yu-Wen Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L21/30604 ,  H01L21/823878 ,  H01L21/76224 ,  H01L21/823821 ,  H01L22/12

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

公开(公告)号：US11823945B2

公开(公告)日：2023-11-21

申请号：US16876287

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wang-Hua Lin ,  Chun-Liang Tai ,  Chun-Hsiang Fan ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/687 ,  H01L21/67 ,  B08B3/08 ,  B08B3/10

CPC classification number: H01L21/68721 ,  B08B3/08 ,  B08B3/10 ,  H01L21/67051 ,  H01L21/67103 ,  H01L21/68728 ,  H01L21/68735 ,  H01L21/68742

Abstract: A method for cleaning a semiconductor wafer is provided. The method includes placing a semiconductor wafer over a supporter arranged around a central axis of a spin base. The method further includes securing the semiconductor wafer using a clamping member positioned on the supporter. The movement of the semiconductor wafer during the placement of the semiconductor wafer over the supporter is guided by a guiding member located over the clamping member. The method also includes spinning the semiconductor wafer by rotating the spin base about the central axis. In addition, the method includes dispensing a processing liquid over the semiconductor wafer.

公开(公告)号：US11682669B2

公开(公告)日：2023-06-20

申请号：US17446900

申请日：2021-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/31111 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L21/823828

Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

公开(公告)号：US20230163027A1

公开(公告)日：2023-05-25

申请号：US18153832

申请日：2023-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Shian Wei Mao ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L23/5226 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/564

Abstract: In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.

公开(公告)号：US20230041753A1

公开(公告)日：2023-02-09

申请号：US17969396

申请日：2022-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US20220359734A1

公开(公告)日：2022-11-10

申请号：US17814185

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssu-Yu Liao ,  Tsu-Hui Su ,  Chun-Hsiang Fan ,  Yu-Wen Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

公开(公告)号：US11488857B2

公开(公告)日：2022-11-01

申请号：US16906615

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US20220336629A1

公开(公告)日：2022-10-20

申请号：US17858968

申请日：2022-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung TSAI ,  Clement Hsingjen Wann ,  Kuo-Feng Yu ,  Ming-Hsi Yeh ,  Shahaji B. More ,  Yu-Ming Lin

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

公开(公告)号：US20220285209A1

公开(公告)日：2022-09-08

申请号：US17193201

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： U-Ting Chiu ,  Po-Nan Yeh ,  Yu-Shih Wang ,  Chun-Neng Lin ,  Ming-Hsi Yeh

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L23/522

Abstract: A method of forming a semiconductor device includes: forming a semiconductor feature over a substrate, the semiconductor feature includes a conductive region; forming a dielectric layer over the semiconductor feature; patterning the dielectric layer to form a contact opening exposing a top surface of the conductive region; forming a monolayer over the dielectric layer, the top surface of the conductive region remaining exposed; and depositing a conductive material in the contact opening.

公开(公告)号：US11437493B2

公开(公告)日：2022-09-06

申请号：US16690005

申请日：2019-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Clement Hsingjen Wann ,  Kuo-Feng Yu ,  Ming-Hsi Yeh ,  Shahaji B. More ,  Yu-Ming Lin

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.