公开(公告)号：US20120195159A1

公开(公告)日：2012-08-02

申请号：US13389628

申请日：2009-10-23

Applicant: Masanori Kitayoshi ,  Yoshiaki Ebine ,  Atsushi Sugihara ,  Kiwamu Kobayashi ,  Takashi Kono ,  Yasuyuki Nakane ,  Kenshu Maruta

Inventor： Masanori Kitayoshi ,  Yoshiaki Ebine ,  Atsushi Sugihara ,  Kiwamu Kobayashi ,  Takashi Kono ,  Yasuyuki Nakane ,  Kenshu Maruta

IPC: B01F7/00 ,  H01M4/139

CPC classification number: B01F7/285 ,  B01F7/0055 ,  H01M4/139 ,  Y10T29/49115

Abstract: An agitation apparatus (100) has a substantially cylindrically shaped agitation vessel (102); a rotation shaft (150) provided along the central axis of the agitation vessel (102); a substantially cylindrically shaped agitation member (104) having an outer diameter smaller than the inner diameter of the agitation vessel (102) and being fitted to the rotation shaft (150) so as to rotate concentrically with an inner circumferential surface of the agitation vessel (102); and a plurality of through holes (162, 164) formed through the agitation member (104) in radial directions of the agitation member. In the agitation apparatus (100), a gap between the inner circumferential surface of the agitation vessel (102) and the outer circumferential surface of the agitation member (104) is partially varied along a vertical direction of the agitation member (104). For example, the gap between the inner circumferential surface of the agitation vessel (102) and the outer circumferential surface of the agitation member (104) is wider at a lower portion (S2) of the agitation member (104) than at an upper portion (S1) of the agitation member (104).

Abstract translation: 搅拌装置（100）具有基本上圆柱形的搅拌容器（102）; 沿所述搅拌容器（102）的中心轴设置的旋转轴（150）; 大致圆柱形的搅拌构件（104），其具有小于搅拌容器（102）的内径的外径，并且装配到旋转轴（150），以与搅拌容器的内周表面同心地旋转（ 102）; 以及在所述搅拌部件的径向方向上穿过所述搅拌部件（104）形成的多个贯通孔（162,164）。 在搅拌装置（100）中，搅拌容器（102）的内周面与搅拌部件（104）的外周面之间的间隙沿着搅拌部件（104）的上下方向部分变化。 例如，搅拌容器（102）的内周面与搅拌部件（104）的外周面之间的间隙在搅拌部件（104）的下部（S2）处比上部部分 （104）的搅拌器（S1）。

公开(公告)号：US07952926B2

公开(公告)日：2011-05-31

申请号：US12705357

申请日：2010-02-12

Applicant: Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

Inventor： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

IPC: G11C11/34

CPC classification number: G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

Abstract: In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

Abstract translation: 在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接 采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。 因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

公开(公告)号：US07692966B2

公开(公告)日：2010-04-06

申请号：US12153927

申请日：2008-05-28

Applicant: Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

Inventor： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

IPC: G11C11/34 ,  G11C8/00

CPC classification number: G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

Abstract: In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

Abstract translation: 在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接 采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。 因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

公开(公告)号：US07433230B2

公开(公告)日：2008-10-07

申请号：US11411938

申请日：2006-04-27

Applicant: Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

Inventor： Takashi Kono ,  Yuichi Kunori ,  Hironori Iga

IPC: G11C11/34 ,  G11C5/06 ,  G11C7/00 ,  G11C8/99

CPC classification number: G11C16/0491 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

Abstract: In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

Abstract translation: 在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接 采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。 因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

公开(公告)号：US20070008781A1

公开(公告)日：2007-01-11

申请号：US11481782

申请日：2006-07-07

Applicant: Yusuke Jono ,  Takashi Kono ,  Tadaaki Yamauchi

Inventor： Yusuke Jono ,  Takashi Kono ,  Tadaaki Yamauchi

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459

Abstract: Using charges accumulated in a capacitance element connected to a drain side node of a memory cell, data is written in accordance with source side injection method. The capacitance value of the capacitance element is changed in accordance with the value of write data. A non-volatile semiconductor memory device allowing writing of multi-valued data at high speed with high precision is achieved.

Abstract translation: 使用与连接到存储单元的漏极侧节点的电容元件中累积的电荷，根据源侧注入方式写入数据。 电容元件的电容值根据写入数据的值而变化。 实现了以高精度写入多值数据的非易失性半导体存储器件。

公开(公告)号：US07154802B2

公开(公告)日：2006-12-26

申请号：US11493663

申请日：2006-07-27

Applicant: Takashi Kono ,  Hironori Iga

Inventor： Takashi Kono ,  Hironori Iga

IPC: G11C5/14

CPC classification number: G11C29/021 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/2227

Abstract: A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of external potential EXTVDD, and thus the supplying time of external potential EXTVDD can be dynamically changed. When external potential EXTVDD is at the upper limit of specification of product, the supplying time is short, thereby preventing overcharge of memory cells or bit lines. When external potential EXTVDD is at the lower limit of specification of product, the supplying time becomes longer, thereby ensuring a sufficient over-driving time interval. It is possible to ensure the reliability of the memory cells and perform the reading operation throughout the entire range of the specification of product of external potential EXTVDD. Therefore, it is possible to provide a semiconductor memory device capable of performing a reading operation at high speeds while ensuring the reliability.

公开(公告)号：US20060262629A1

公开(公告)日：2006-11-23

申请号：US11493663

申请日：2006-07-27

Applicant: Takashi Kono ,  Hironori Iga

Inventor： Takashi Kono ,  Hironori Iga

IPC: G11C5/14

CPC classification number: G11C29/021 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/2227

Abstract: A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of external potential EXTVDD, and thus the supplying time of external potential EXTVDD can be dynamically changed. When external potential EXTVDD is at the upper limit of specification of product, the supplying time is short, thereby preventing overcharge of memory cells or bit lines. When external potential EXTVDD is at the lower limit of specification of product, the supplying time becomes longer, thereby ensuring a sufficient over-driving time interval. It is possible to ensure the reliability of the memory cells and perform the reading operation throughout the entire range of the specification of product of external potential EXTVDD. Therefore, it is possible to provide a semiconductor memory device capable of performing a reading operation at high speeds while ensuring the reliability.

Abstract translation: 用于监视外部电位EXTVDD和可变延迟电路的监视电路根据外部电位EXTVDD的电位电平确定信号ZODACT处于L电平的时间间隔，因此可以动态地改变外部电位EXTVDD的供电时间。 当外部电位EXTVDD处于产品规格的上限时，供电时间短，从而防止存储单元或位线的过充电。 当外部电位EXTVDD处于产品规格的下限时，供电时间变长，从而确保足够的过驱动时间间隔。 可以确保存储单元的可靠性，并在外部电位EXTVDD的产品规格的整个范围内执行读取操作。 因此，可以提供能够在确保可靠性的同时高速执行读取操作的半导体存储器件。

公开(公告)号：US06903922B2

公开(公告)日：2005-06-07

申请号：US10387397

申请日：2003-03-14

Applicant: Mitsunori Sano ,  Takashi Kono

Inventor： Mitsunori Sano ,  Takashi Kono

IPC: H01G9/00 ,  H01G9/012 ,  H01G13/00 ,  H01G4/228 ,  H01G9/04

CPC classification number: H01G9/012 ,  H01G2/02 ,  H01G4/236

Abstract: A chip type capacitor which has improved bond strength between an anode lead wire and an anode terminal and enhanced reliability, and a method for preparing the chip type capacitor and an anode terminal. The chip type capacitor has a solid electrolytic capacitor element including an element body having an anode body, a dielectric and a cathode body, and an anode lead wire partially extending from the anode body of the element body. An anode terminal is electrically connected to the portion of the anode lead wire extending from the anode body. This extending portion of the anode lead wire has about 75% or more of its periphery, in the direction substantially perpendicular to the extending direction of the anode lead wire, covered with solidified matter resulting from solidification of a melt, thereby bonding the anode terminal and the anode lead wire to each other.

Abstract translation: 具有改善阳极引线和阳极端子之间的接合强度并提高可靠性的芯片型电容器，以及制造芯片型电容器和阳极端子的方法。 片式电容器具有固体电解电容器元件，其包括具有阳极体，电介质和阴极体的元件体以及从元件体的阳极体部分延伸的阳极引线。 阳极端子电连接到从阳极体延伸的阳极引线的部分。 阳极引线的该延伸部分在大致垂直于阳极引线的延伸方向的方向上具有大约75％或更多的周边，被固化的熔体所固化的物质覆盖，从而将阳极端子和 阳极引线相互连接。

公开(公告)号：US06850049B2

公开(公告)日：2005-02-01

申请号：US10642216

申请日：2003-08-18

Applicant: Takashi Kono

Inventor： Takashi Kono

IPC: H01L27/04 ,  G05F3/16 ,  G11C5/14 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/00 ,  H03K3/354 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/0948

CPC classification number: G11C5/147

Abstract: A semiconductor device according to the present invention has a configuration that a resistance section is connected to only one of a current-mirror section forming a voltage conversion circuit and an output section. With this configuration, it is possible to determine the temperature dependency of an output voltage according to S factors of transistors forming one of the current-mirror section and the output section and a resistance value of the resistance section, and to suppress manufacturing irregularities caused by irregularities of the transistors between the two sections and those among a plurality of resistance materials.

Abstract translation: 根据本发明的半导体器件具有电阻部分仅连接到形成电压转换电路的电流镜部分和输出部分中的一个的结构。 根据该结构，能够根据形成电流镜部和输出部中的一个的晶体管的S因子和电阻部的电阻值来确定输出电压的温度依赖性，并且抑制由 两部分之间的晶体管的不规则和多个电阻材料之间的晶体管的不规则性。

公开(公告)号：US06768698B2

公开(公告)日：2004-07-27

申请号：US10255667

申请日：2002-09-27

Applicant: Takashi Kono

Inventor： Takashi Kono

IPC: G11C722

CPC classification number: G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C2207/2227

Abstract: A repeater receives an internal clock distributed from a DLL circuit irrespective of a data reading operation and outputs a DLL clock to a data output circuit and a data strobe signal output circuit in response to an internal signal only in the data reading operation. The data strobe signal output circuit receives the internal clock and the DLL clock, generates a data strobe signal in synchronization with the internal clock, and outputs the generated data strobe signal in synchronization with the DLL clock. As a result, a semiconductor memory device attains further reduction of power consumption during active-standby and a secure supply of the internal clock to a prescribed circuit.

Abstract translation: 中继器接收从DLL电路分配的内部时钟，与数据读取操作无关，并且仅在数据读取操作中响应于内部信号而将DLL时钟输出到数据输出电路和数据选通信号输出电路。 数据选通信号输出电路接收内部时钟和DLL时钟，与内部时钟同步产生数据选通信号，并与DLL时钟同步输出生成的数据选通信号。 结果，半导体存储器件在主动待机期间进一步降低功耗并且将内部时钟可靠地提供给规定的电路。