公开(公告)号：US07968910B2

公开(公告)日：2011-06-28

申请号：US12103301

申请日：2008-04-15

申请人： Xiangdong Chen ,  Thomas W. Dyer ,  Haining S. Yang

发明人： Xiangdong Chen ,  Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L21/02 ,  H01L27/12

CPC分类号： H01L21/823807 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.

摘要翻译： 提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。 在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。 第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。 基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。 可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。 基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。 然后可以在嵌入的硅区域中形成源区和漏区。 硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。

公开(公告)号：US07911001B2

公开(公告)日：2011-03-22

申请号：US11778045

申请日：2007-07-15

申请人： Kyoung Woo Lee ,  Ja Hum Ku ,  Taehoon Lee ,  Seung-Man Choi ,  Thomas W. Dyer

发明人： Kyoung Woo Lee ,  Ja Hum Ku ,  Taehoon Lee ,  Seung-Man Choi ,  Thomas W. Dyer

IPC分类号： H01L21/311 ,  H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7843

摘要： CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.

摘要翻译： 提供CMOS（互补金属氧化物半导体）制造技术以形成具有非重叠，自对准的双应力衬垫结构的DSL（双应力衬垫）半导体器件。

公开(公告)号：US07750429B2

公开(公告)日：2010-07-06

申请号：US11748521

申请日：2007-05-15

申请人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Zhijiong Luo ,  Haining S. Yang

IPC分类号： H01L29/78

CPC分类号： H01L21/76229 ,  H01L21/3086 ,  H01L21/823878

摘要： A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure.

摘要翻译： 从衬垫层形成基座，使得底座的两个边缘与植入的孔的边界重合。 通过沉积保形介电层在基座上形成延伸基座。 扩展基座的面积暴露在下方的半导体表面凹陷到凹陷深度。 包括至少一个井内隔离沟槽的其它沟槽被光刻图案化。 在反应离子蚀刻之后，形成阱间隔离沟槽和至少一个阱间隔离沟槽。 与现有技术的结构相比，由于较深的底面，间隙隔离沟槽的宽度可能会降低。 在井间隔离结构下面的p阱和n阱之间的边界与井间隔离结构的中间自对准。

公开(公告)号：US07728364B2

公开(公告)日：2010-06-01

申请号：US11624931

申请日：2007-01-19

申请人： Huilong Zhu ,  Thomas W. Dyer

发明人： Huilong Zhu ,  Thomas W. Dyer

IPC分类号： H01L39/06

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/7853

摘要： The present invention provides structures and methods for a transistor formed on a V-shaped groove. The V-shaped groove contains two crystallographic facets joined by a ridge. The facets have different crystallographic orientations than what a semiconductor substrate normally provides such as the substrate orientation or orientations orthogonal to the substrate orientation. Unlike the prior art, the V-shaped groove is formed self-aligned to the shallow trench isolation, eliminating the need to precisely align the V-shaped grooves with lithographic means. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a V-shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

摘要翻译： 本发明提供了形成在V形槽上的晶体管的结构和方法。 V形槽包含两个通过脊连接的结晶面。 这些刻面具有与半导体衬底通常提供的不同的晶体取向，例如衬底取向或与衬底取向正交的取向。 与现有技术不同，V形槽形成为与浅沟槽隔离自对准，从而不需要将V形槽与光刻装置精确对准。 新面的电特性，特别是增强的载流子迁移率被用于增强晶体管的性能。 在具有被连接以形成V形轮廓的小平面上的通道的晶体管中，电流沿连接小面的脊的方向流动，以避免在电流方向上的任何拐点。

公开(公告)号：US20090267196A1

公开(公告)日：2009-10-29

申请号：US12500396

申请日：2009-07-09

申请人： Thomas W. Dyer ,  Haining S. Yang

发明人： Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L29/04

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/04 ,  H01L29/66795 ,  H01L29/7853

摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

摘要翻译： 本发明涉及高性能三维（3D）场效应晶体管（FET）。 具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。 更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。 附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。

公开(公告)号：US07582516B2

公开(公告)日：2009-09-01

申请号：US11422443

申请日：2006-06-06

申请人： Thomas W. Dyer ,  Sunfei Fang ,  Judson R. Holt

发明人： Thomas W. Dyer ,  Sunfei Fang ,  Judson R. Holt

IPC分类号： H01L21/00 ,  H01L21/76

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823857 ,  H01L29/1037 ,  H01L29/78 ,  H01L29/7853

摘要： The present invention relates to a semiconductor substrate comprising at least first and second device regions. The first device region has a substantially planar surface oriented along one of a first set of equivalent crystal planes, and the second device region contains a protruding semiconductor structure having multiple intercepting surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, a first field effect transistor (FET) can be formed at the first device region, which comprises a channel that extends along the substantially planar surface of the first device region. A second, complementary FET can be formed at the second device region, while the second, complementary FET comprises a channel that extends along the multiple intercepting surfaces of the protruding semiconductor structure at the second device region.

摘要翻译： 本发明涉及包括至少第一和第二器件区域的半导体衬底。 第一器件区域具有沿着第一组等效晶面中的一个取向的基本平坦的表面，并且第二器件区域包含具有沿第二不同组的等效晶面取向的多个截止面的突出半导体结构。 可以使用这种半导体衬底形成半导体器件结构。 具体地，可以在第一器件区域处形成第一场效应晶体管（FET），该第一器件区域包括沿着第一器件区域的基本平坦的表面延伸的沟道。 第二互补FET可以形成在第二器件区域，而第二互补FET包括在第二器件区域沿着突出半导体结构的多个截止表面延伸的沟道。

公开(公告)号：US07560382B2

公开(公告)日：2009-07-14

申请号：US11467712

申请日：2006-08-28

申请人： Haining Yang ,  Thomas W. Dyer

发明人： Haining Yang ,  Thomas W. Dyer

IPC分类号： H01L21/44

CPC分类号： H01L27/1104 ,  H01L27/0207 ,  H01L27/11

摘要： The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.

摘要翻译： 本发明涉及一种半导体器件，其包括第一和第二有源器件区域，其位于半导体衬底中并且通过其间的隔离区彼此隔离，而半导体器件包括嵌入在隔离中的第一导电互连结构 并且将第一有源器件区域与第二有源器件区域连接。 半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一导电互连结构将SRAM单元的下拉晶体管与其上拉晶体管交叉连接。 导电互连优选地包括掺杂多晶硅，并且可以通过包括光刻图案，蚀刻和多晶硅沉积的处理步骤形成。

公开(公告)号：US07550330B2

公开(公告)日：2009-06-23

申请号：US11564352

申请日：2006-11-29

申请人： Thomas W. Dyer ,  Zhijiong Luo ,  Jack A. Mandelman

发明人： Thomas W. Dyer ,  Zhijiong Luo ,  Jack A. Mandelman

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/78615 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78618

摘要： A semiconductor structure is provided that has body contacts that are located at the edges of the device channel and a buried insulating region under the device channel that is shallower than the buried insulating regions under the source/drain junctions. A method of forming such a semiconductor structure is also described. The inventive method provides for self-alignment of the various features mentioned above with the gate conductor of the structure.

摘要翻译： 提供半导体结构，其具有位于器件沟道的边缘处的体接触以及在器件沟道下方比在源极/漏极结下方的掩埋绝缘区域浅的掩埋绝缘区域。 还描述了形成这种半导体结构的方法。 本发明的方法提供了上述各种特征与结构的栅极导体的自对准。

公开(公告)号：US07528451B2

公开(公告)日：2009-05-05

申请号：US11692402

申请日：2007-03-28

申请人： Huilong Zhu ,  Thomas W. Dyer ,  Haining S. Yang

发明人： Huilong Zhu ,  Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L29/76

CPC分类号： H01L21/28044 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/78

摘要： A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFET active semiconductor regions are separated by an isolation region. An NFET gate extends in a first direction over the NFET active semiconductor region. A PFET gate extends in the first direction over the PFET active semiconductor region. A diffusion barrier is sandwiched between the NFET gate and the PFET gate. A continuous layer extends continuously in the first direction over the NFET gate and the PFET gate. The continuous layer contacts top surfaces of the NFET gate and the PFET gate and the continuous layer includes at least one of a semiconductor, a metal or a conductive compound including a metal.

摘要翻译： 为包括具有NFET有源半导体区域的n型场效应晶体管（“NFET”）和具有PFET有源半导体区域的p型场效应晶体管（“PFET”）的晶体管对，提供栅极导体，其中 NFET和PFET有源半导体区域被隔离区隔开。 NFET栅极在NFET有源半导体区域上的第一方向上延伸。 PFET栅极在PFET有源半导体区域上沿第一方向延伸。 扩散势垒夹在NFET栅极和PFET栅极之间。 连续层在NFET栅极和PFET栅极上在第一方向上连续延伸。 连续层接触NFET栅极和PFET栅极的顶表面，并且连续层包括半导体，金属或包括金属的导电化合物中的至少一种。

公开(公告)号：US07517767B2

公开(公告)日：2009-04-14

申请号：US11559574

申请日：2006-11-14

申请人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan

发明人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan

IPC分类号： H01L21/336

CPC分类号： H01L21/823871 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

摘要： Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.

摘要翻译： 本发明的实施例提供一种形成与半导体器件接触的导电柱的方法。 该方法包括形成覆盖半导体器件的保护层; 选择性地将开口向下蚀刻穿过保护层到达半导体器件的接触区域，该开口远离半导体器件的保护区域; 并用导电材料填充开口以形成导电柱。 一个实施例还可以包括直接在半导体器件的顶部上形成电介质衬垫，以及在电介质衬垫的顶部上形成保护层。 本发明的实施例还提供由其制成的半导体器件。