公开(公告)号：US06781417B1

公开(公告)日：2004-08-24

申请号：US10282459

申请日：2002-10-29

申请人： Binh Quang Le ,  Lee Cleveland ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Lee Cleveland ,  Pau-Ling Chen

IPC分类号： H03K19185

CPC分类号： G05F3/242 ,  H03K19/018507

摘要： According to one exemplary embodiment, a buffer circuit is configured to receive a supply voltage and an input reference voltage, the buffer circuit has a first FET operating in saturation region where the source of the first FET is coupled to the output reference voltage. The first FET can be configured, for example, as an open-loop voltage follower and, by way of example, a first resistor can be used to couple the source of the first FET to the output reference voltage. A tracking circuit is connected to the buffer circuit. The tracking circuit comprises a second FET also operating in saturation region where the drain of the second FET is coupled to the output reference voltage. Both the first and second FETs can be, for example, depletion mode transistors.

摘要翻译： 根据一个示例性实施例，缓冲电路被配置为接收电源电压和输入参考电压，所述缓冲电路具有在饱和区域中工作的第一FET，其中第一FET的源极耦合到输出参考电压。 第一FET可以被配置为例如开环电压跟随器，并且作为示例，可以使用第一电阻器将第一FET的源极耦合到输出参考电压。 跟踪电路连接到缓冲电路。 跟踪电路包括也在饱和区域工作的第二FET，其中第二FET的漏极耦合到输出参考电压。 第一和第二FET都可以是例如耗尽型晶体管。

公开(公告)号：US06700815B2

公开(公告)日：2004-03-02

申请号：US10119273

申请日：2002-04-08

申请人： Binh Quang Le ,  Michael Chung ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Michael Chung ,  Pau-Ling Chen

IPC分类号： G11C1604

CPC分类号： G11C16/3431 ,  G11C16/0475 ,  G11C16/3418

摘要： A flash memory array having multiple dual bit memory cells divided into section attached to a wordline and a pair of reference cells logically associated with each section. A method of reprogramming a section or sections of words that are required to be changed includes inputting allowed changes to the flash memory array, reading word or words to be changed in each section, programming bits in word or words to be changed in each section, refreshing previously programmed bits in the word or words that are changed, refreshing previously programmed bits in the word or words changed in each section, refreshing previously programmed bits in the remaining word or words in each section and refreshing previously programmed in each pair of reference cells in the section in which changes have been made.

摘要翻译： 一种闪存阵列，其具有被分成连接到字线的部分和与每个部分逻辑关联的一对参考单元的多个双位存储器单元。 重新编程需要改变的单词部分或方式的方法包括：输入对闪存阵列的允许的改变，读取每个部分中要改变的单词或单词，在每个部分中改变单词或单词中的位， 刷新改变的单词中的先前编程的位，刷新每个部分中改变的单词中改变的先前编程的比特，刷新每个部分中剩余单词或先前编程的比特，并刷新以前在每对参考单元中编程 在作出改变的部分。

公开(公告)号：US06424570B1

公开(公告)日：2002-07-23

申请号：US09892189

申请日：2001-06-26

申请人： Binh Q. Le ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Pau-Ling Chen

IPC分类号： G11C1604

CPC分类号： H02M3/073

摘要： A system is described for generating a charge pump voltage for flash memory operations, wherein a supply voltage detection circuit (e.g., analog to digital converter, digital thermometer) is configured to detect a supply voltage value and generate one or more supply voltage level detection signals associated therewith. The system further includes a charge pump circuit comprising one or more stages operable to receive a supply voltage and generate the charge pump output voltage having a value greater than the supply voltage, and a charge pump compensation circuit operably coupled to the supply voltage detection circuit and the charge pump circuit. The charge pump compensation circuit is operable to receive the one or more output signals from the supply voltage detection circuit and modulate a capacitive loading associated with the charge pump circuit based on the one or more output signals, thereby creating an improved low power charge pump which uses a modulated pumping capacitance to compensate for fluctuations of the input power supply (for example, VCC), to produce a slow ripple and low noise output which may be used as a pumped voltage for various mode operations (e.g., erase, program modes) of memory cells.

摘要翻译： 描述了一种用于产生用于闪速存储器操作的电荷泵电压的系统，其中电源电压检测电路（例如，模数转换器，数字温度计）被配置为检测电源电压值并产生一个或多个电源电压电平检测信号 相关联。 该系统还包括电荷泵电路，其包括一个或多个级，可操作以接收电源电压并产生具有大于电源电压的值的电荷泵输出电压;以及电荷泵补偿电路，其可操作地耦合到电源电压检测电路和 电荷泵电路。 电荷泵补偿电路可操作以从电源电压检测电路接收一个或多个输出信号，并且基于该一个或多个输出信号调制与电荷泵电路相关联的电容性负载，从而产生改进的低功率电荷泵， 使用调制的泵浦电容来补偿输入电源的波动（例如VCC），以产生慢波纹和低噪声输出，其可用作用于各种模式操作（例如擦除，编程模式）的泵浦电压， 的记忆细胞。

公开(公告)号：US06292399B1

公开(公告)日：2001-09-18

申请号：US09609897

申请日：2000-07-03

申请人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk

发明人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk

IPC分类号： G11C1606

CPC分类号： G11C16/28

摘要： Control circuitry and a method for generating an accurate drain voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Select gate transistors are provided which have their conduction path being coupled between a power supply voltage and a drain of one of the selected memory core cells. A differential amplifier circuit is responsive to a bitline voltage corresponding to a drain voltage of the selected memory core cells and a reference voltage for generating a select gate voltage. The select gate voltage is decreased when the bitline voltage is higher than a target voltage and is increased when the bitline voltage is lower than the target voltage. A source follower circuit is responsive to the select gate voltage for generating the bitline voltage which is maintained at the target voltage. The control gates of the select gate transistors are connected to receive the select gate voltage for maintaining the voltage at the drain of the selected memory core cells to be approximately constant.

摘要翻译： 提供控制电路和在读操作模式期间为半导体存储器件中的选定存储核心单元产生准确的漏极电压的方法。 提供选择栅极晶体管，其导通路径耦合在所选存储核心单元之一的电源电压和漏极之间。 差分放大器电路响应于对应于所选择的存储器单元的漏极电压的位线电压和用于产生选择栅极电压的参考电压。 当位线电压高于目标电压时，选择栅极电压降低，并且当位线电压低于目标电压时，选择栅极电压增加。 源极跟随器电路响应选择栅极电压以产生保持在目标电压的位线电压。 选择栅极晶体管的控制栅极被连接以接收选择栅极电压，以将所选择的存储器核心单元的漏极处的电压保持为大致恒定。

公开(公告)号：US06208561B1

公开(公告)日：2001-03-27

申请号：US09593303

申请日：2000-06-13

申请人： Binh Q. Le ,  Kazuhiro Kurihara ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Kazuhiro Kurihara ,  Pau-Ling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/08

摘要： An apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages as selected wordlines and block select lines are provided. A decoding structure separately applies a first boosted voltage to the wordline N-well region and a second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region. The decoding structure further applies a third boosted voltage to the select gate N-well region and a fourth boosted voltage to the block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region. As a consequence, an accurate voltage can be created quickly at the selected wordline since its capacitive loading path is very small.

摘要翻译： 提供了一种用于降低闪存X解码器中的电容负载以便精确地将电压控制为选择的字线和块选择线的装置和方法。 解码结构分别将第一升压电压施加到字线N阱区域，并将第二升压电压施加到所选择的字线，以便由于与字线N阱区域相关联的重电容性负载而减小所选字线上的容性负载。 解码结构还将第三升压电压施加到选择栅极N阱区域，并将第四升压电压施加到块选择线，以便由于与选择栅极N相关联的重电容负载而减小块选择线上的电容负载， 井区。 因此，由于其电容加载路径非常小，所以可以在所选字线处快速创建精确的电压。

公开(公告)号：US06177322B1

公开(公告)日：2001-01-23

申请号：US09177817

申请日：1998-10-23

申请人： Narbeh Derhacobian ,  Pau-Ling Chen ,  Hao Fang ,  Timothy Thurgate

发明人： Narbeh Derhacobian ,  Pau-Ling Chen ,  Hao Fang ,  Timothy Thurgate

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L29/1033 ,  H01L29/41775

摘要： A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, providing a thick gate oxide layer, employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants, and forming contacts to the source and drain regions at a minimum distance from the gate.

摘要翻译： 形成表现出高选通二极管击穿电压的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩盖来自常规场注入的高电压接头来提供高门控二极管击穿电压，从常规阈值调整注入屏蔽源极/漏极区域，提供厚栅极氧化物层，采用非常轻掺杂的n型注入 代替常规的n +和LDD植入物，并且在与栅极最小距离处形成与源区和漏区的接触。

公开(公告)号：US5978267A

公开(公告)日：1999-11-02

申请号：US175647

申请日：1998-10-20

申请人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

发明人： Pau-Ling Chen ,  Michael Van Buskirk ,  Shane C. Hollmer ,  Michael S. C. Chung ,  Binh Quang Le ,  Vincent Leung ,  Shoichi Kawamura ,  Masaru Yano

IPC分类号： G11C16/02 ,  G11C7/12 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C7/12

摘要： In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.

摘要翻译： 在非易失性存储器件（例如NAND闪速存储器件100）的编程中，将正偏置电压Vbias施加到位线44以将相应的存储器栅极44a设置为编程状态。 在另一实施例中，通过使用串联连接的两个电阻器56和58分压选择漏极栅极电压Vcc来获得正偏置电压Vbias。

公开(公告)号：US5939928A

公开(公告)日：1999-08-17

申请号：US914196

申请日：1997-08-19

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer

IPC分类号： G11C5/14 ,  G11C8/08 ,  G11C16/12 ,  H03K17/16

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C8/08

摘要： In a high voltage pass gate suitable for use as a block decoder in a flash memory circuit, the boosting of the block decoder's internal nodes is performed using coupling capacitors and boost transistors which are decoupled from the high capacitance pass gate node. The block decoder uses three internal block decoder nodes. Each of the three nodes is held to ground by a corresponding discharge transistor when the block is unselected. Each of the three nodes of a selected block is discharged to a normal supply voltage by a corresponding diode-connected regulation transistor when the high voltage supply is turned off after a programming operation has finished. Each of the three nodes has a separate coupling capacitor associated with it. One of the nodes is connected to the gates of the high voltage pass transistors, this node has high capacitance. The remaining two nodes have relatively small coupling capacitors. These other two nodes are capacitively coupling during opposite phases of a clock, and one of them controls a boost transistor which charges the high capacitance pass gate node. Two embodiments are presented, one having one less transistor than the other.

摘要翻译： 在适用于闪速存储器电路中的块解码器的高压通道中，使用从高电容通过栅极节点去耦的耦合电容器和升压晶体管来执行块解码器的内部节点的升压。 块解码器使用三个内部块解码器节点。 当块未被选择时，三个节点中的每一个被相应的放电晶体管保持接地。 当编程操作完成后，当高压电源关闭时，所选块的三个节点中的每一个都通过相应的二极管连接的调节晶体管放电到正常的电源电压。 三个节点中的每一个具有与其相关联的单独的耦合电容器。 节点中的一个连接到高电压通过晶体管的栅极，该节点具有高电容。 剩余的两个节点具有相对较小的耦合电容器。 这些另外两个节点在时钟的相反相位期间电容耦合，并且其中一个节点控制对高电容通过门节点充电的升压晶体管。 呈现了两个实施例，一个具有比另一个更少的晶体管。

公开(公告)号：US5821800A

公开(公告)日：1998-10-13

申请号：US799074

申请日：1997-02-11

申请人： Binh Quang Le ,  Shoichi Kawamura ,  Pau-Ling Chen ,  Shane Hollmer

发明人： Binh Quang Le ,  Shoichi Kawamura ,  Pau-Ling Chen ,  Shane Hollmer

IPC分类号： H03K5/02 ,  H03K3/356 ,  H03K17/10 ,  H03K19/0185 ,  H03K1/175 ,  H03K19/003

CPC分类号： H03K17/102 ,  H03K3/356113

摘要： A high-voltage level shifter includes one or more complementary NMOS/PMOS series intermediate transistor pairs to divide the high-voltage supply range into two or more sub-ranges. The level shifter has a differential structure with complementary NMOS input transistors. Cross-coupled PMOS output transistors provide complementary outputs. The complementary NMOS/PMOS series intermediate transistor pairs separate the NMOS input transistor drains from the PMOS output transistor drains. In order to divide the high voltage range into h subranges, h-1 complementary NMOS/PMOS series intermediate transistor pairs are used each being biased by monotonically increasing fixed intermediate voltages. In a shared-bias embodiment, each complementary NMOS/PMOS series intermediate transistor pair is biased by a single corresponding intermediate voltage. In a split-bias embodiment, each complementary NMOS/PMOS series intermediate transistor pair is biased by a corresponding NMOS bias voltage and a corresponding PMOS bias voltage, in which the NMOS bias voltage is higher than the PMOS bias voltage by the sum or the NMOS threshold voltage and the PMOS threshold voltage. In another aspect, the N-wells of the PMOS transistors are tied to an upwardly vertically adjacent intermediate voltage in the shared-bias embodiments, and are tied to an upwardly vertically adjacent NMOS bias voltage in the split-bias embodiments. In a twin tub embodiment for very high voltage applications, the P-wells of the NMOS transistors are tied to a downwardly vertically adjacent intermediate voltage in the shared-bias embodiments, and are tied to a downwardly vertically adjacent PMOS bias voltage for the split-bias embodiments.

摘要翻译： 高电压电平移位器包括一个或多个互补的NMOS / PMOS串联中间晶体管对，以将高电压电源范围分成两个或更多个子范围。 电平移位器具有互补NMOS输入晶体管的差分结构。 交叉耦合PMOS输出晶体管提供互补输出。 互补的NMOS / PMOS系列中间晶体管对将NMOS输入晶体管漏极与PMOS输出晶体管漏极分离。 为了将高电压范围划分为h个子范围，使用h-1互补的NMOS / PMOS系列中间晶体管对，通过单调增加固定中间电压来偏置。 在共享偏置实施例中，每个互补NMOS / PMOS系列中间晶体管对由单个对应的中间电压偏置。 在分离偏置实施例中，每个互补NMOS / PMOS串联中间晶体管对由相应的NMOS偏置电压和相应的PMOS偏置电压偏置，其中NMOS偏置电压高于PMOS偏置电压乘以和或NMOS 阈值电压和PMOS阈值电压。 在另一方面，PMOS晶体管的N阱在共享偏压实施例中被连接到向上垂直相邻的中间电压，并且在分离偏压实施例中被连接到向上垂直相邻的NMOS偏置电压。 在用于非常高电压应用的双槽实施例中，NMOS晶体管的P阱在共享偏压实施例中被连接到向下垂直相邻的中间电压，并且被连接到向下垂直相邻的PMOS偏置电压， 偏压实施例。

公开(公告)号：US5815438A

公开(公告)日：1998-09-29

申请号：US810170

申请日：1997-02-28

申请人： Sameer S. Haddad ,  Pau-Ling Chen

发明人： Sameer S. Haddad ,  Pau-Ling Chen

IPC分类号： G11C16/26 ,  G11C16/06

CPC分类号： G11C16/3427 ,  G11C16/26

摘要： There is provided an improved method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a floating gate device is used as a select gate. A first positive pulse voltage having a ramp-rate characteristic on its leading edge is applied to the drain of the floating gate device during the read operation. Simultaneously, a second positive pulse voltage is applied to the control gate of the floating gate device during the read operation so as to overlap the first positive pulse voltage.

摘要翻译： 提供了一种在浮动栅极器件用作选择栅极的NAND存储器架构中在读取操作期间消除热载波干扰的改进方法。 在读取操作期间，在其前沿具有斜率特性的第一正脉冲电压被施加到浮动栅极器件的漏极。 同时，在读取操作期间，第二正脉冲电压施加到浮动栅极器件的控制栅极，以便与第一正脉冲电压重叠。