公开(公告)号：US12160953B2

公开(公告)日：2024-12-03

申请号：US17992933

申请日：2022-11-23

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

公开(公告)号：US20240248264A1

公开(公告)日：2024-07-25

申请号：US18623035

申请日：2024-04-01

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: G02B6/42 ,  G02B6/12 ,  H01L23/498 ,  H01L25/065

CPC classification number: G02B6/4206 ,  G02B6/12004 ,  G02B6/4293 ,  H01L23/49816 ,  H01L25/0652

Abstract: Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.

公开(公告)号：US20240237209A9

公开(公告)日：2024-07-11

申请号：US17986899

申请日：2022-11-15

Applicant: Unimicron Technology Corp.

Inventor： Ping-Tsung Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/34 ,  H05K3/40

CPC classification number: H05K1/114 ,  H05K1/024 ,  H05K3/3442 ,  H05K3/4007 ,  H05K2201/0195 ,  H05K2203/041

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

公开(公告)号：US20240138063A1

公开(公告)日：2024-04-25

申请号：US17986899

申请日：2022-11-15

Applicant: Unimicron Technology Corp.

Inventor： Ping-Tsung Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/34 ,  H05K3/40

CPC classification number: H05K1/114 ,  H05K1/024 ,  H05K3/3442 ,  H05K3/4007 ,  H05K2201/0195 ,  H05K2203/041

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

公开(公告)号：US20240138059A1

公开(公告)日：2024-04-25

申请号：US17992933

申请日：2022-11-23

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K1/11 ,  H05K3/4644 ,  H05K2203/041

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

公开(公告)号：US11764120B2

公开(公告)日：2023-09-19

申请号：US17155094

申请日：2021-01-22

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Pei-Chi Chen ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/49827

Abstract: A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.

公开(公告)号：US11665832B2

公开(公告)日：2023-05-30

申请号：US17234805

申请日：2021-04-20

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/20 ,  H05K3/36 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46 ,  H05K3/02

CPC classification number: H05K3/46 ,  H05K3/022 ,  H05K3/386 ,  H05K3/4038

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

公开(公告)号：US20230067112A1

公开(公告)日：2023-03-02

申请号：US17983396

申请日：2022-11-09

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  John Hon-Shing Lau ,  Pu-Ju Lin ,  Wei-Ci Ye ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: F28D15/04 ,  F28D15/02 ,  F28F3/10 ,  B23P15/26 ,  F28F21/08

Abstract: A vapor chamber structure includes a thermally conductive shell, a capillary structure layer, and a working fluid. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion and the second thermally conductive portion are a thermally conductive plate that is integrally formed, and the thermally conductive shell is formed by folding the thermally conductive plate in half and then sealing the thermally conductive plate. The first thermally conductive portion has at least one first cavity, the second thermally conductive portion has at least one second cavity. At least one sealed chamber is defined between the thermally conductive plate, the first cavity and the second cavity. A pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.

公开(公告)号：US11476234B2

公开(公告)日：2022-10-18

申请号：US16846429

申请日：2020-04-13

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L25/075 ,  H01L33/62 ,  H01L33/00 ,  H01L33/52

Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.

公开(公告)号：US11460255B2

公开(公告)日：2022-10-04

申请号：US17113332

申请日：2020-12-07

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Pu-Ju Lin ,  Ying-Chu Chen ,  Wei-Ci Ye ,  Chi-Hai Kuo ,  Cheng-Ta Ko

IPC: B23P15/26 ,  F28D15/04 ,  C23F17/00 ,  H05K7/20 ,  H01L23/427

Abstract: A vapor chamber device and a manufacturing method are disclosed. The vapor chamber has a housing and multiple independent chambers. The housing includes two shells opposite to each other. The independent chambers are formed between the two shells. Each independent chamber contains a working fluid and has at least one diversion bump and a capillary structure. The diversion bump is formed on an inner surface of the second shell, and the capillary structure is mounted on the diversion bump. When the vapor chamber device is vertically mounted to a heat source, the independent chambers at an upper portion of the vapor chamber device still contain the working fluid. The working fluid in the independent chambers may not all flow to a bottom of the vapor chamber device. Therefore, a contact area between the working fluid and the heat source is increased and heat dissipation efficiency is improved.