公开(公告)号：US20190206879A1

公开(公告)日：2019-07-04

申请号：US15884063

申请日：2018-01-30

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Shu-Ru Wang ,  Wei-Chi Lee ,  Chun-Yen Tseng

IPC: H01L27/11 ,  H01L27/092 ,  G11C11/41 ,  H01L23/522 ,  H01L27/02

Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.

公开(公告)号：US20190206459A1

公开(公告)日：2019-07-04

申请号：US15992130

申请日：2018-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Lu ,  Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shou-Sian Chen ,  Koji Nii ,  Yuichiro Ishii

IPC: G11C8/16 ,  G11C8/08 ,  G11C7/12 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C8/16 ,  G11C5/025 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11

Abstract: A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.

公开(公告)号：US09941288B2

公开(公告)日：2018-04-10

申请号：US15635190

申请日：2017-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US20170317091A1

公开(公告)日：2017-11-02

申请号：US15635190

申请日：2017-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US20170317090A1

公开(公告)日：2017-11-02

申请号：US15635165

申请日：2017-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US09799650B2

公开(公告)日：2017-10-24

申请号：US15043614

申请日：2016-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207

Abstract: A semiconductor layout structure includes at least a first signal line and a pair of Vss lines. The first signal line and the pair of Vss lines are extended along a first direction, and the Vss lines are arranged along a second direction. The first direction and the second direction are perpendicular to each other. The Vss lines are arranged at respective two sides of the first signal line.

公开(公告)号：US20170200717A1

公开(公告)日：2017-07-13

申请号：US15043614

申请日：2016-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/088 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207

Abstract: A semiconductor layout structure includes at least a first signal line and a pair of Vss lines. The first signal line and the pair of Vss lines are extended along a first direction, and the Vss lines are arranged along a second direction. The first direction and the second direction are perpendicular to each other. The Vss lines are arranged at respective two sides of the first signal line.

公开(公告)号：US08966410B2

公开(公告)日：2015-02-24

申请号：US14065443

申请日：2013-10-29

Applicant: United Microelectronics Corp.

Inventor： Chia-Wei Huang ,  Ming-Jui Chen ,  Chun-Hsien Huang

IPC: G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00 ,  G03F1/76 ,  H01L21/311 ,  G03F1/70 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: G03F1/76 ,  G03F1/70 ,  G06F17/5068 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.

Abstract translation: 一种用于制造半导体布局的方法包括提供具有多个线图案的第一布局和具有多个连接图案的第二布局，所述多个连接图案定义与线图案中的连接图案重叠的至少第一分割图案， 将第一待分割图案分割成与连接图案重叠的第一待分割图案，分解第一布局以形成第三布局和第四布局，并将第三布局和其他布局输出到 第一掩模和第二掩模。

公开(公告)号：US08741507B1

公开(公告)日：2014-06-03

申请号：US13742361

申请日：2013-01-16

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Huang ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Ting-Cheng Tseng

IPC: G03F1/70

CPC classification number: G03F1/70

Abstract: A method for separating photomask pattern, including the following steps: first, a layout pattern is provided, wherein the layout pattern is defined to have at least one critical pattern and at least one non-critical pattern. Then, a first split process is performed to separate the critical pattern into a plurality of first patterns and a plurality of second patterns. A second split process is performed to separate the non-critical pattern into a plurality of third patterns and a plurality of fourth patterns. Finally, the first patterns and the third patterns are output to a first photomask, and the second patterns and the fourth patterns are output to a second photomask.

Abstract translation: 一种用于分离光掩模图案的方法，包括以下步骤：首先，提供布局图案，其中布局图案被定义为具有至少一个关键图案和至少一个非关键图案。 然后，执行第一分割处理以将关键图案分离成多个第一图案和多个第二图案。 执行第二分割处理以将非关键图案分离成多个第三图案和多个第四图案。 最后，将第一图案和第三图案输出到第一光掩模，并将第二图案和第四图案输出到第二光掩模。

公开(公告)号：US20140045105A1

公开(公告)日：2014-02-13

申请号：US14065443

申请日：2013-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Huang ,  Ming-Jui Chen ,  Chun-Hsien Huang

IPC: G03F1/76

CPC classification number: G03F1/76 ,  G03F1/70 ,  G06F17/5068 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.

Abstract translation: 一种用于制造半导体布局的方法包括提供具有多个线图案的第一布局和具有多个连接图案的第二布局，所述多个连接图案定义与线图案中的连接图案重叠的至少第一分割图案， 将第一待分割图案分割成与连接图案重叠的第一待分割图案，分解第一布局以形成第三布局和第四布局，并将第三布局和其他布局输出到 第一掩模和第二掩模。